module arbiter(clock, reset_n, enable_one, enable_two, rw_one, rw_two, ack_one, ack_two, ram_ack, chip_select, bridge_select);
	input clock, reset_n;
	input enable_one, enable_two, rw_one, rw_two;
	input ram_ack;
	output ack_one, ack_two;
	output chip_select, bridge_select;
	
	reg [2:0]	present_state, next_state;
	
	parameter 	s_WAIT_REQUEST = 3'd0,
				s_ISSUE_ONE = 3'd1,
				s_WAIT_DEASSERT_ONE = 3'd2,
				s_CYCLE_DELAY = 3'd3,
				s_ISSUE_TWO = 3'd4,
				s_WAIT_DEASSERT_TWO = 3'd5;
				
	/* State Transitions */
	always @(*)
	begin
		case (present_state)
			s_WAIT_REQUEST:
				if (enable_one)
					next_state <= s_ISSUE_ONE;
				else if (enable_two)
					next_state <= s_ISSUE_TWO;
				else
					next_state <= s_WAIT_REQUEST;
					
			s_ISSUE_ONE:
				if (ram_ack)
					next_state <= s_WAIT_DEASSERT_ONE;
				else
					next_state <= s_ISSUE_ONE;
				
			s_WAIT_DEASSERT_ONE:
				if (enable_one)
					next_state <= s_WAIT_DEASSERT_ONE;
				else
					next_state <= s_CYCLE_DELAY;
					
			s_CYCLE_DELAY:
				if (enable_two)
					next_state <= s_ISSUE_TWO;
				else
					next_state <= s_WAIT_REQUEST;
					
			s_ISSUE_TWO:
				if (ram_ack)
					next_state <= s_WAIT_DEASSERT_TWO;
				else
					next_state <= s_ISSUE_TWO;	
				
			s_WAIT_DEASSERT_TWO:
				if (enable_two)
					next_state <= s_WAIT_DEASSERT_TWO;
				else
					next_state <= s_WAIT_REQUEST;
								
			default:
				next_state <= s_WAIT_REQUEST;
		endcase
	end
	
	/* State registers */
	always @(posedge clock or negedge reset_n)
	begin
		if (~reset_n)
			present_state <= s_WAIT_REQUEST;
		else
			present_state <= next_state;
	end
	
	/* Output logic */
	assign ack_one = (present_state == s_WAIT_DEASSERT_ONE);
	assign ack_two = (present_state == s_WAIT_DEASSERT_TWO);
	assign chip_select = (present_state == s_ISSUE_ONE) || (present_state == s_ISSUE_TWO);
	assign bridge_select = (present_state == s_ISSUE_TWO) || (present_state == s_WAIT_DEASSERT_TWO);
endmodule
