# custom_system

generated 2009.07.20.17:31:24

## Overview

clk | custom_system

Processor
cpu Nios II 9.0
Peripherals
cpu altera_nios2 9.0
onchip_mem altera_avalon_onchip_memory2 9.0
switches altera_up_avalon_parallel_port 9.0
red_LEDs altera_up_avalon_parallel_port 9.0

| cpu
instruction_master | data_master
cpu |  |
jtag_debug_module | 0x0a000000 | 0x0a000000
onchip_mem |  |
s1 | 0x00000000 | 0x00000000
switches |  |
avalon_parallel_port_slave |  | 0x10000040
red_LEDs |  |
avalon_parallel_port_slave |  | 0x10000000

## clk

clock_source v9.0

## Parameters
clockFrequency | 50000000
clockFrequencyKnown | true

## Software Assignments (none)

## cpu

altera_nios2 v9.0

clk | clk | cpu
clk
|  | instruction_master | onchip_mem
|  | s1
|  | data_master
|  | s1
|  | data_master | switches
|  | avalon_parallel_port_slave
|  | data_master | red_LEDs
|  | avalon_parallel_port_slave

## Parameters
userDefinedSettings |
setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_shadowRegisterSetsPresent | false
setting_preciseSlaveAccessErrorException | false
setting_preciseIllegalMemAccessException | false
setting_preciseDivisionErrorException | false
setting_performanceCounter | false
setting_perfCounterWidth | _32
setting_numShadowRegisterSets | 1
setting_illegalMemAccessDetection | false
setting_illegalInstructionsTrap | false
setting_fullWaveformSignals | false
setting_extraExceptionInfo | false
setting_exportPCB | false
setting_eicPresent | false
setting_debugSimGen | false
setting_clearXBitsLDNonBypass | true
setting_branchPredictionType | Automatic
setting_bit31BypassDCache | true
setting_bhtPtrSz | _8
setting_bhtIndexPcOnly | false
setting_avalonDebugPortPresent | false
setting_autoAssignNumShadowRegisterSets | true
setting_alwaysEncrypt | true
setting_allowFullAddressRange | false
setting_activateTrace | true
setting_activateTestEndChecker | false
setting_activateMonitors | true
setting_activateModelChecker | false
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
resetSlave | onchip_mem.s1
resetOffset | 0
muldiv_multiplierType | EmbeddedMulFast
muldiv_divider | false
mpu_useLimit | false
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mpu_minInstRegionSize | _12
mpu_minDataRegionSize | _12
mpu_enabled | false
mmu_uitlbNumEntries | _4
mmu_udtlbNumEntries | _6
mmu_tlbPtrSz | _7
mmu_tlbNumWays | _16
mmu_processIDNumBits | _8
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
mmu_TLBMissExcSlave |
mmu_TLBMissExcOffset | 0
manuallyAssignCpuID | false
impl | Small
icache_size | _4096
icache_ramBlockType | Automatic
icache_numTCIM | _0
icache_burstType | None
exceptionSlave | onchip_mem.s1
exceptionOffset | 32
debug_triggerArming | true
debug_level | Level1
debug_jtagInstanceID | 0
debug_embeddedPLL | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
debug_OCIOnchipTrace | _128
dcache_size | _2048
dcache_ramBlockType | Automatic
dcache_omitDataMaster | false
dcache_numTCDM | _0
dcache_lineSize | _32
dcache_bursts | false
cpuReset | false
cpuID | 0
clockFrequency | 50000000
breakSlave | cpu.jtag_debug_module
breakOffset | 32

## Software Assignments
CPU_IMPLEMENTATION | "small"
CPU_FREQ | 50000000u
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
DCACHE_LINE_SIZE | 0
DCACHE_LINE_SIZE_LOG2 | 0
DCACHE_SIZE | 0
FLUSHDA_SUPPORTED |
HAS_JMPI_INSTRUCTION |
EXCEPTION_ADDR | 0x20
RESET_ADDR | 0x0
BREAK_ADDR | 0xa000020
HAS_DEBUG_STUB |
HAS_DEBUG_CORE | 1
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x0
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
INST_ADDR_WIDTH | 28
DATA_ADDR_WIDTH | 29

## onchip_mem

altera_avalon_onchip_memory2 v9.0

clk | clk | onchip_mem
clk1
cpu | instruction_master
s1
data_master
s1

## Parameters
allowInSystemMemoryContentEditor | false
blockType | AUTO
dataWidth | 32
dualPort | false
initMemContent | true
initializationFileName | onchip_mem
instanceID | NONE
memorySize | 4096
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | false
useShallowMemBlocks | false
writable | true

## Software Assignments
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
INIT_CONTENTS_FILE | "onchip_mem"
NON_DEFAULT_INIT_FILE_ENABLED | 0
GUI_RAM_BLOCK_TYPE | "Automatic"
WRITABLE | 1
DUAL_PORT | 0
SIZE_VALUE | 4096u
SIZE_MULTIPLE | 1
CONTENTS_INFO | ""
RAM_BLOCK_TYPE | "Auto"
INIT_MEM_CONTENT | 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
INSTANCE_ID | "NONE"
READ_DURING_WRITE_MODE | "DONT_CARE"

## switches

altera_up_avalon_parallel_port v9.0

clk | clk | switches
clock_reset
cpu | data_master
avalon_parallel_port_slave

## Parameters
board | DE1
preset | Slider Switches
pushbuttons | false
leds | Green
sevensegs | 3 to 0
gpio | GPIO 0 (JP1)
DW | 10
direction | Input only
capture | false
edge | Rising
irq | false
irq_type | Level
AUTO_CLOCK_RESET_CLOCK_RATE | 50000000

## Software Assignments (none)

## red_LEDs

altera_up_avalon_parallel_port v9.0

clk | clk | red_LEDs
clock_reset
cpu | data_master
avalon_parallel_port_slave

## Parameters
board | DE1
preset | LEDs
pushbuttons | false
leds | Red
sevensegs | 3 to 0
gpio | GPIO 0 (JP1)
DW | 10
direction | Output only
capture | false
edge | Rising
irq | false
irq_type | Level
AUTO_CLOCK_RESET_CLOCK_RATE | 50000000

## Software Assignments (none)

generation took 0.00 seconds
rendering took 3.08 seconds