module signaltap(CLOCK_50, KEY, LEDG);
	input 			CLOCK_50;
	input 	[1:0]	KEY;
	output 	[7:0]	LEDG;
	
	reg 	[7:0]	shift_reg_bits;
	wire			enable;

	reg		[1:0]	ps,ns;
	parameter	A = 2'd0, B = 2'd1, C = 2'd2;
	
	/* Datapath - a simple shift register */
	always@(posedge CLOCK_50 or negedge KEY[0])
	begin
		if (~KEY[0])
			shift_reg_bits <= 8'd1;
		else if (enable) 
		begin
			shift_reg_bits[7:1] <= shift_reg_bits[6:0];
			shift_reg_bits[0] <= shift_reg_bits[7];
		end
	end
	assign LEDG = shift_reg_bits;
	
	/* Control FSM - State transitions */
	always@(*)
		case (ps)
			A: 	if (~KEY[1])
					ns <= B;
				else
					ns <= A;
				
			B: 	ns <= C;
				
			C: 	if (KEY[1])
					ns <= A;
				else
					ns <= C;
			default: 
					ns <= 2'bxx;
		endcase
	
	/* State Registers */
	always@(posedge CLOCK_50 or negedge KEY[0])
	begin
		if (~KEY[0])
			ps <= A;
		else
			ps <= ns;
	end	
	
	/* FSM output */
	assign enable = (ps == B);

endmodule
