module chat_room(CLOCK_50, KEY, SRAM_DQ, SRAM_ADDR,	SRAM_LB_N, SRAM_UB_N, SRAM_CE_N, SRAM_OE_N,	SRAM_WE_N);
	input 				CLOCK_50;
	input 		[0:0] 	KEY;
	inout		[15:0]	SRAM_DQ;		// SRAM Data bus 16 Bits
	output		[17:0]	SRAM_ADDR;		// SRAM Address bus 18 Bits
	output				SRAM_LB_N;		// SRAM Low-byte Data Mask 
	output				SRAM_UB_N;		// SRAM High-byte Data Mask 
	output				SRAM_CE_N;		// SRAM Chip chipselect
	output				SRAM_OE_N;		// SRAM Output chipselect
	output				SRAM_WE_N;		// SRAM Write chipselect	
	
	wire bridge_select, chip_select, rw_one, rw_two, ack_one, ack_two, enable_one, enable_two;
	wire [18:0] address_one;
	wire [18:0] address_two;
	wire [31:0] writedata_one;
	wire [31:0] writedata_two;
	wire [31:0]	readdata;
	reg [31:0]	readdata_reg;
	wire [3:0]	be_one;
	wire [3:0]	be_two;
	wire vcc;
	
	assign vcc = 1'b1;
	
	// Instantiate the dual processor system.
	dual_processor_system my_system(
	   // 1) global signals:
		.clk(CLOCK_50),
		.reset_n(KEY[0]),

	   // the_bridge_one
		.acknowledge_to_the_bridge_one(ack_one),
		.address_from_the_bridge_one(address_one),
		.bus_enable_from_the_bridge_one(enable_one),
		.byte_enable_from_the_bridge_one(be_one),
		.irq_to_the_bridge_one(vcc),
		.read_data_to_the_bridge_one(readdata_reg),
		.rw_from_the_bridge_one(rw_one),
		.write_data_from_the_bridge_one(writedata_one),

	   // the_bridge_two
		.acknowledge_to_the_bridge_two(ack_two),
		.address_from_the_bridge_two(address_two),
		.bus_enable_from_the_bridge_two(enable_two),
		.byte_enable_from_the_bridge_two(be_two),
		.irq_to_the_bridge_two(vcc),
		.read_data_to_the_bridge_two(readdata_reg),
		.rw_from_the_bridge_two(rw_two),
		.write_data_from_the_bridge_two(writedata_two)
	 );

    arbiter my_arbiter(
		.clock(CLOCK_50),
		.reset_n(KEY[0]),
		.enable_one(enable_one),
		.enable_two(enable_two),
		.rw_one(rw_one),
		.rw_two(rw_two),
		.ack_one(ack_one),
		.ack_two(ack_two),
		.ram_ack(ram_ack),
		.chip_select(chip_select),
		.bridge_select(bridge_select)
		);
    
    // Register data read from SRAM.
    always @(posedge CLOCK_50)
    begin
		if (ram_ack)
			readdata_reg <= readdata;
	end
	            
	sram my_sram(
		.clk(CLOCK_50),
		.reset_n(KEY[0]),
		.address( (bridge_select == 1'b1) ? address_two : address_one ),
		.byte_enable((bridge_select == 1'b1) ? be_two : be_one),
		.bus_enable(chip_select),
		.rw((bridge_select == 1'b1) ? (rw_two) : (rw_one)),
		.write_data((bridge_select == 1'b1) ? writedata_two : writedata_one),
		.read_data(readdata),
		.SRAM_DQ(SRAM_DQ),
		.SRAM_ADDR(SRAM_ADDR),
		.SRAM_LB_N(SRAM_LB_N),
		.SRAM_UB_N(SRAM_UB_N),
		.SRAM_CE_N(SRAM_CE_N),
		.SRAM_OE_N(SRAM_OE_N),
		.SRAM_WE_N(SRAM_WE_N),

		.acknowledge(ram_ack)
	);                             
endmodule
