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//GENERATION: STANDARD
//VERSION: WM1.0


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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module bridge_one_avalon_slave_arbitrator (
                                            // inputs:
                                             bridge_one_avalon_slave_irq,
                                             bridge_one_avalon_slave_readdata,
                                             bridge_one_avalon_slave_waitrequest,
                                             clk,
                                             cpu_one_data_master_address_to_slave,
                                             cpu_one_data_master_byteenable,
                                             cpu_one_data_master_read,
                                             cpu_one_data_master_waitrequest,
                                             cpu_one_data_master_write,
                                             cpu_one_data_master_writedata,
                                             reset_n,

                                            // outputs:
                                             bridge_one_avalon_slave_address,
                                             bridge_one_avalon_slave_byteenable,
                                             bridge_one_avalon_slave_chipselect,
                                             bridge_one_avalon_slave_irq_from_sa,
                                             bridge_one_avalon_slave_read,
                                             bridge_one_avalon_slave_readdata_from_sa,
                                             bridge_one_avalon_slave_reset,
                                             bridge_one_avalon_slave_waitrequest_from_sa,
                                             bridge_one_avalon_slave_write,
                                             bridge_one_avalon_slave_writedata,
                                             cpu_one_data_master_granted_bridge_one_avalon_slave,
                                             cpu_one_data_master_qualified_request_bridge_one_avalon_slave,
                                             cpu_one_data_master_read_data_valid_bridge_one_avalon_slave,
                                             cpu_one_data_master_requests_bridge_one_avalon_slave,
                                             d1_bridge_one_avalon_slave_end_xfer,
                                             registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave
                                          )
;

  output  [ 16: 0] bridge_one_avalon_slave_address;
  output  [  3: 0] bridge_one_avalon_slave_byteenable;
  output           bridge_one_avalon_slave_chipselect;
  output           bridge_one_avalon_slave_irq_from_sa;
  output           bridge_one_avalon_slave_read;
  output  [ 31: 0] bridge_one_avalon_slave_readdata_from_sa;
  output           bridge_one_avalon_slave_reset;
  output           bridge_one_avalon_slave_waitrequest_from_sa;
  output           bridge_one_avalon_slave_write;
  output  [ 31: 0] bridge_one_avalon_slave_writedata;
  output           cpu_one_data_master_granted_bridge_one_avalon_slave;
  output           cpu_one_data_master_qualified_request_bridge_one_avalon_slave;
  output           cpu_one_data_master_read_data_valid_bridge_one_avalon_slave;
  output           cpu_one_data_master_requests_bridge_one_avalon_slave;
  output           d1_bridge_one_avalon_slave_end_xfer;
  output           registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave;
  input            bridge_one_avalon_slave_irq;
  input   [ 31: 0] bridge_one_avalon_slave_readdata;
  input            bridge_one_avalon_slave_waitrequest;
  input            clk;
  input   [ 19: 0] cpu_one_data_master_address_to_slave;
  input   [  3: 0] cpu_one_data_master_byteenable;
  input            cpu_one_data_master_read;
  input            cpu_one_data_master_waitrequest;
  input            cpu_one_data_master_write;
  input   [ 31: 0] cpu_one_data_master_writedata;
  input            reset_n;

  wire    [ 16: 0] bridge_one_avalon_slave_address;
  wire             bridge_one_avalon_slave_allgrants;
  wire             bridge_one_avalon_slave_allow_new_arb_cycle;
  wire             bridge_one_avalon_slave_any_bursting_master_saved_grant;
  wire             bridge_one_avalon_slave_any_continuerequest;
  wire             bridge_one_avalon_slave_arb_counter_enable;
  reg              bridge_one_avalon_slave_arb_share_counter;
  wire             bridge_one_avalon_slave_arb_share_counter_next_value;
  wire             bridge_one_avalon_slave_arb_share_set_values;
  wire             bridge_one_avalon_slave_beginbursttransfer_internal;
  wire             bridge_one_avalon_slave_begins_xfer;
  wire    [  3: 0] bridge_one_avalon_slave_byteenable;
  wire             bridge_one_avalon_slave_chipselect;
  wire             bridge_one_avalon_slave_end_xfer;
  wire             bridge_one_avalon_slave_firsttransfer;
  wire             bridge_one_avalon_slave_grant_vector;
  wire             bridge_one_avalon_slave_in_a_read_cycle;
  wire             bridge_one_avalon_slave_in_a_write_cycle;
  wire             bridge_one_avalon_slave_irq_from_sa;
  wire             bridge_one_avalon_slave_master_qreq_vector;
  wire             bridge_one_avalon_slave_non_bursting_master_requests;
  wire             bridge_one_avalon_slave_read;
  wire    [ 31: 0] bridge_one_avalon_slave_readdata_from_sa;
  reg              bridge_one_avalon_slave_reg_firsttransfer;
  wire             bridge_one_avalon_slave_reset;
  reg              bridge_one_avalon_slave_slavearbiterlockenable;
  wire             bridge_one_avalon_slave_slavearbiterlockenable2;
  wire             bridge_one_avalon_slave_unreg_firsttransfer;
  wire             bridge_one_avalon_slave_waitrequest_from_sa;
  wire             bridge_one_avalon_slave_waits_for_read;
  wire             bridge_one_avalon_slave_waits_for_write;
  wire             bridge_one_avalon_slave_write;
  wire    [ 31: 0] bridge_one_avalon_slave_writedata;
  wire             cpu_one_data_master_arbiterlock;
  wire             cpu_one_data_master_arbiterlock2;
  wire             cpu_one_data_master_continuerequest;
  wire             cpu_one_data_master_granted_bridge_one_avalon_slave;
  wire             cpu_one_data_master_qualified_request_bridge_one_avalon_slave;
  wire             cpu_one_data_master_read_data_valid_bridge_one_avalon_slave;
  reg              cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register;
  wire             cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register_in;
  wire             cpu_one_data_master_requests_bridge_one_avalon_slave;
  wire             cpu_one_data_master_saved_grant_bridge_one_avalon_slave;
  reg              d1_bridge_one_avalon_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_bridge_one_avalon_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p1_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register;
  wire             registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave;
  wire    [ 19: 0] shifted_address_to_bridge_one_avalon_slave_from_cpu_one_data_master;
  wire             wait_for_bridge_one_avalon_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~bridge_one_avalon_slave_end_xfer;
    end


  assign bridge_one_avalon_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_one_data_master_qualified_request_bridge_one_avalon_slave));
  //assign bridge_one_avalon_slave_readdata_from_sa = bridge_one_avalon_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign bridge_one_avalon_slave_readdata_from_sa = bridge_one_avalon_slave_readdata;

  assign cpu_one_data_master_requests_bridge_one_avalon_slave = ({cpu_one_data_master_address_to_slave[19] , 19'b0} == 20'h0) & (cpu_one_data_master_read | cpu_one_data_master_write);
  //assign bridge_one_avalon_slave_waitrequest_from_sa = bridge_one_avalon_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign bridge_one_avalon_slave_waitrequest_from_sa = bridge_one_avalon_slave_waitrequest;

  //registered rdv signal_name registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave assignment, which is an e_assign
  assign registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave = cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register_in;

  //bridge_one_avalon_slave_arb_share_counter set values, which is an e_mux
  assign bridge_one_avalon_slave_arb_share_set_values = 1;

  //bridge_one_avalon_slave_non_bursting_master_requests mux, which is an e_mux
  assign bridge_one_avalon_slave_non_bursting_master_requests = cpu_one_data_master_requests_bridge_one_avalon_slave;

  //bridge_one_avalon_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign bridge_one_avalon_slave_any_bursting_master_saved_grant = 0;

  //bridge_one_avalon_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign bridge_one_avalon_slave_arb_share_counter_next_value = bridge_one_avalon_slave_firsttransfer ? (bridge_one_avalon_slave_arb_share_set_values - 1) : |bridge_one_avalon_slave_arb_share_counter ? (bridge_one_avalon_slave_arb_share_counter - 1) : 0;

  //bridge_one_avalon_slave_allgrants all slave grants, which is an e_mux
  assign bridge_one_avalon_slave_allgrants = |bridge_one_avalon_slave_grant_vector;

  //bridge_one_avalon_slave_end_xfer assignment, which is an e_assign
  assign bridge_one_avalon_slave_end_xfer = ~(bridge_one_avalon_slave_waits_for_read | bridge_one_avalon_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_bridge_one_avalon_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_bridge_one_avalon_slave = bridge_one_avalon_slave_end_xfer & (~bridge_one_avalon_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //bridge_one_avalon_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign bridge_one_avalon_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_bridge_one_avalon_slave & bridge_one_avalon_slave_allgrants) | (end_xfer_arb_share_counter_term_bridge_one_avalon_slave & ~bridge_one_avalon_slave_non_bursting_master_requests);

  //bridge_one_avalon_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bridge_one_avalon_slave_arb_share_counter <= 0;
      else if (bridge_one_avalon_slave_arb_counter_enable)
          bridge_one_avalon_slave_arb_share_counter <= bridge_one_avalon_slave_arb_share_counter_next_value;
    end


  //bridge_one_avalon_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bridge_one_avalon_slave_slavearbiterlockenable <= 0;
      else if ((|bridge_one_avalon_slave_master_qreq_vector & end_xfer_arb_share_counter_term_bridge_one_avalon_slave) | (end_xfer_arb_share_counter_term_bridge_one_avalon_slave & ~bridge_one_avalon_slave_non_bursting_master_requests))
          bridge_one_avalon_slave_slavearbiterlockenable <= |bridge_one_avalon_slave_arb_share_counter_next_value;
    end


  //cpu_one/data_master bridge_one/avalon_slave arbiterlock, which is an e_assign
  assign cpu_one_data_master_arbiterlock = bridge_one_avalon_slave_slavearbiterlockenable & cpu_one_data_master_continuerequest;

  //bridge_one_avalon_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign bridge_one_avalon_slave_slavearbiterlockenable2 = |bridge_one_avalon_slave_arb_share_counter_next_value;

  //cpu_one/data_master bridge_one/avalon_slave arbiterlock2, which is an e_assign
  assign cpu_one_data_master_arbiterlock2 = bridge_one_avalon_slave_slavearbiterlockenable2 & cpu_one_data_master_continuerequest;

  //bridge_one_avalon_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign bridge_one_avalon_slave_any_continuerequest = 1;

  //cpu_one_data_master_continuerequest continued request, which is an e_assign
  assign cpu_one_data_master_continuerequest = 1;

  assign cpu_one_data_master_qualified_request_bridge_one_avalon_slave = cpu_one_data_master_requests_bridge_one_avalon_slave & ~((cpu_one_data_master_read & ((|cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register))) | ((~cpu_one_data_master_waitrequest) & cpu_one_data_master_write));
  //cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register_in = cpu_one_data_master_granted_bridge_one_avalon_slave & cpu_one_data_master_read & ~bridge_one_avalon_slave_waits_for_read & ~(|cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register);

  //shift register p1 cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register = {cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register, cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register_in};

  //cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register <= 0;
      else 
        cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register <= p1_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register;
    end


  //local readdatavalid cpu_one_data_master_read_data_valid_bridge_one_avalon_slave, which is an e_mux
  assign cpu_one_data_master_read_data_valid_bridge_one_avalon_slave = cpu_one_data_master_read_data_valid_bridge_one_avalon_slave_shift_register;

  //bridge_one_avalon_slave_writedata mux, which is an e_mux
  assign bridge_one_avalon_slave_writedata = cpu_one_data_master_writedata;

  //master is always granted when requested
  assign cpu_one_data_master_granted_bridge_one_avalon_slave = cpu_one_data_master_qualified_request_bridge_one_avalon_slave;

  //cpu_one/data_master saved-grant bridge_one/avalon_slave, which is an e_assign
  assign cpu_one_data_master_saved_grant_bridge_one_avalon_slave = cpu_one_data_master_requests_bridge_one_avalon_slave;

  //allow new arb cycle for bridge_one/avalon_slave, which is an e_assign
  assign bridge_one_avalon_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign bridge_one_avalon_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign bridge_one_avalon_slave_master_qreq_vector = 1;

  //~bridge_one_avalon_slave_reset assignment, which is an e_assign
  assign bridge_one_avalon_slave_reset = ~reset_n;

  assign bridge_one_avalon_slave_chipselect = cpu_one_data_master_granted_bridge_one_avalon_slave;
  //bridge_one_avalon_slave_firsttransfer first transaction, which is an e_assign
  assign bridge_one_avalon_slave_firsttransfer = bridge_one_avalon_slave_begins_xfer ? bridge_one_avalon_slave_unreg_firsttransfer : bridge_one_avalon_slave_reg_firsttransfer;

  //bridge_one_avalon_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign bridge_one_avalon_slave_unreg_firsttransfer = ~(bridge_one_avalon_slave_slavearbiterlockenable & bridge_one_avalon_slave_any_continuerequest);

  //bridge_one_avalon_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bridge_one_avalon_slave_reg_firsttransfer <= 1'b1;
      else if (bridge_one_avalon_slave_begins_xfer)
          bridge_one_avalon_slave_reg_firsttransfer <= bridge_one_avalon_slave_unreg_firsttransfer;
    end


  //bridge_one_avalon_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign bridge_one_avalon_slave_beginbursttransfer_internal = bridge_one_avalon_slave_begins_xfer;

  //bridge_one_avalon_slave_read assignment, which is an e_mux
  assign bridge_one_avalon_slave_read = cpu_one_data_master_granted_bridge_one_avalon_slave & cpu_one_data_master_read;

  //bridge_one_avalon_slave_write assignment, which is an e_mux
  assign bridge_one_avalon_slave_write = cpu_one_data_master_granted_bridge_one_avalon_slave & cpu_one_data_master_write;

  assign shifted_address_to_bridge_one_avalon_slave_from_cpu_one_data_master = cpu_one_data_master_address_to_slave;
  //bridge_one_avalon_slave_address mux, which is an e_mux
  assign bridge_one_avalon_slave_address = shifted_address_to_bridge_one_avalon_slave_from_cpu_one_data_master >> 2;

  //d1_bridge_one_avalon_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_bridge_one_avalon_slave_end_xfer <= 1;
      else 
        d1_bridge_one_avalon_slave_end_xfer <= bridge_one_avalon_slave_end_xfer;
    end


  //bridge_one_avalon_slave_waits_for_read in a cycle, which is an e_mux
  assign bridge_one_avalon_slave_waits_for_read = bridge_one_avalon_slave_in_a_read_cycle & bridge_one_avalon_slave_waitrequest_from_sa;

  //bridge_one_avalon_slave_in_a_read_cycle assignment, which is an e_assign
  assign bridge_one_avalon_slave_in_a_read_cycle = cpu_one_data_master_granted_bridge_one_avalon_slave & cpu_one_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = bridge_one_avalon_slave_in_a_read_cycle;

  //bridge_one_avalon_slave_waits_for_write in a cycle, which is an e_mux
  assign bridge_one_avalon_slave_waits_for_write = bridge_one_avalon_slave_in_a_write_cycle & bridge_one_avalon_slave_waitrequest_from_sa;

  //bridge_one_avalon_slave_in_a_write_cycle assignment, which is an e_assign
  assign bridge_one_avalon_slave_in_a_write_cycle = cpu_one_data_master_granted_bridge_one_avalon_slave & cpu_one_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = bridge_one_avalon_slave_in_a_write_cycle;

  assign wait_for_bridge_one_avalon_slave_counter = 0;
  //bridge_one_avalon_slave_byteenable byte enable port mux, which is an e_mux
  assign bridge_one_avalon_slave_byteenable = (cpu_one_data_master_granted_bridge_one_avalon_slave)? cpu_one_data_master_byteenable :
    -1;

  //assign bridge_one_avalon_slave_irq_from_sa = bridge_one_avalon_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign bridge_one_avalon_slave_irq_from_sa = bridge_one_avalon_slave_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //bridge_one/avalon_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module bridge_two_avalon_slave_arbitrator (
                                            // inputs:
                                             bridge_two_avalon_slave_irq,
                                             bridge_two_avalon_slave_readdata,
                                             bridge_two_avalon_slave_waitrequest,
                                             clk,
                                             cpu_two_data_master_address_to_slave,
                                             cpu_two_data_master_byteenable,
                                             cpu_two_data_master_read,
                                             cpu_two_data_master_waitrequest,
                                             cpu_two_data_master_write,
                                             cpu_two_data_master_writedata,
                                             reset_n,

                                            // outputs:
                                             bridge_two_avalon_slave_address,
                                             bridge_two_avalon_slave_byteenable,
                                             bridge_two_avalon_slave_chipselect,
                                             bridge_two_avalon_slave_irq_from_sa,
                                             bridge_two_avalon_slave_read,
                                             bridge_two_avalon_slave_readdata_from_sa,
                                             bridge_two_avalon_slave_reset,
                                             bridge_two_avalon_slave_waitrequest_from_sa,
                                             bridge_two_avalon_slave_write,
                                             bridge_two_avalon_slave_writedata,
                                             cpu_two_data_master_granted_bridge_two_avalon_slave,
                                             cpu_two_data_master_qualified_request_bridge_two_avalon_slave,
                                             cpu_two_data_master_read_data_valid_bridge_two_avalon_slave,
                                             cpu_two_data_master_requests_bridge_two_avalon_slave,
                                             d1_bridge_two_avalon_slave_end_xfer,
                                             registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave
                                          )
;

  output  [ 16: 0] bridge_two_avalon_slave_address;
  output  [  3: 0] bridge_two_avalon_slave_byteenable;
  output           bridge_two_avalon_slave_chipselect;
  output           bridge_two_avalon_slave_irq_from_sa;
  output           bridge_two_avalon_slave_read;
  output  [ 31: 0] bridge_two_avalon_slave_readdata_from_sa;
  output           bridge_two_avalon_slave_reset;
  output           bridge_two_avalon_slave_waitrequest_from_sa;
  output           bridge_two_avalon_slave_write;
  output  [ 31: 0] bridge_two_avalon_slave_writedata;
  output           cpu_two_data_master_granted_bridge_two_avalon_slave;
  output           cpu_two_data_master_qualified_request_bridge_two_avalon_slave;
  output           cpu_two_data_master_read_data_valid_bridge_two_avalon_slave;
  output           cpu_two_data_master_requests_bridge_two_avalon_slave;
  output           d1_bridge_two_avalon_slave_end_xfer;
  output           registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave;
  input            bridge_two_avalon_slave_irq;
  input   [ 31: 0] bridge_two_avalon_slave_readdata;
  input            bridge_two_avalon_slave_waitrequest;
  input            clk;
  input   [ 19: 0] cpu_two_data_master_address_to_slave;
  input   [  3: 0] cpu_two_data_master_byteenable;
  input            cpu_two_data_master_read;
  input            cpu_two_data_master_waitrequest;
  input            cpu_two_data_master_write;
  input   [ 31: 0] cpu_two_data_master_writedata;
  input            reset_n;

  wire    [ 16: 0] bridge_two_avalon_slave_address;
  wire             bridge_two_avalon_slave_allgrants;
  wire             bridge_two_avalon_slave_allow_new_arb_cycle;
  wire             bridge_two_avalon_slave_any_bursting_master_saved_grant;
  wire             bridge_two_avalon_slave_any_continuerequest;
  wire             bridge_two_avalon_slave_arb_counter_enable;
  reg              bridge_two_avalon_slave_arb_share_counter;
  wire             bridge_two_avalon_slave_arb_share_counter_next_value;
  wire             bridge_two_avalon_slave_arb_share_set_values;
  wire             bridge_two_avalon_slave_beginbursttransfer_internal;
  wire             bridge_two_avalon_slave_begins_xfer;
  wire    [  3: 0] bridge_two_avalon_slave_byteenable;
  wire             bridge_two_avalon_slave_chipselect;
  wire             bridge_two_avalon_slave_end_xfer;
  wire             bridge_two_avalon_slave_firsttransfer;
  wire             bridge_two_avalon_slave_grant_vector;
  wire             bridge_two_avalon_slave_in_a_read_cycle;
  wire             bridge_two_avalon_slave_in_a_write_cycle;
  wire             bridge_two_avalon_slave_irq_from_sa;
  wire             bridge_two_avalon_slave_master_qreq_vector;
  wire             bridge_two_avalon_slave_non_bursting_master_requests;
  wire             bridge_two_avalon_slave_read;
  wire    [ 31: 0] bridge_two_avalon_slave_readdata_from_sa;
  reg              bridge_two_avalon_slave_reg_firsttransfer;
  wire             bridge_two_avalon_slave_reset;
  reg              bridge_two_avalon_slave_slavearbiterlockenable;
  wire             bridge_two_avalon_slave_slavearbiterlockenable2;
  wire             bridge_two_avalon_slave_unreg_firsttransfer;
  wire             bridge_two_avalon_slave_waitrequest_from_sa;
  wire             bridge_two_avalon_slave_waits_for_read;
  wire             bridge_two_avalon_slave_waits_for_write;
  wire             bridge_two_avalon_slave_write;
  wire    [ 31: 0] bridge_two_avalon_slave_writedata;
  wire             cpu_two_data_master_arbiterlock;
  wire             cpu_two_data_master_arbiterlock2;
  wire             cpu_two_data_master_continuerequest;
  wire             cpu_two_data_master_granted_bridge_two_avalon_slave;
  wire             cpu_two_data_master_qualified_request_bridge_two_avalon_slave;
  wire             cpu_two_data_master_read_data_valid_bridge_two_avalon_slave;
  reg              cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register;
  wire             cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register_in;
  wire             cpu_two_data_master_requests_bridge_two_avalon_slave;
  wire             cpu_two_data_master_saved_grant_bridge_two_avalon_slave;
  reg              d1_bridge_two_avalon_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_bridge_two_avalon_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p1_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register;
  wire             registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave;
  wire    [ 19: 0] shifted_address_to_bridge_two_avalon_slave_from_cpu_two_data_master;
  wire             wait_for_bridge_two_avalon_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~bridge_two_avalon_slave_end_xfer;
    end


  assign bridge_two_avalon_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_two_data_master_qualified_request_bridge_two_avalon_slave));
  //assign bridge_two_avalon_slave_readdata_from_sa = bridge_two_avalon_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign bridge_two_avalon_slave_readdata_from_sa = bridge_two_avalon_slave_readdata;

  assign cpu_two_data_master_requests_bridge_two_avalon_slave = ({cpu_two_data_master_address_to_slave[19] , 19'b0} == 20'h0) & (cpu_two_data_master_read | cpu_two_data_master_write);
  //assign bridge_two_avalon_slave_waitrequest_from_sa = bridge_two_avalon_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign bridge_two_avalon_slave_waitrequest_from_sa = bridge_two_avalon_slave_waitrequest;

  //registered rdv signal_name registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave assignment, which is an e_assign
  assign registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave = cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register_in;

  //bridge_two_avalon_slave_arb_share_counter set values, which is an e_mux
  assign bridge_two_avalon_slave_arb_share_set_values = 1;

  //bridge_two_avalon_slave_non_bursting_master_requests mux, which is an e_mux
  assign bridge_two_avalon_slave_non_bursting_master_requests = cpu_two_data_master_requests_bridge_two_avalon_slave;

  //bridge_two_avalon_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign bridge_two_avalon_slave_any_bursting_master_saved_grant = 0;

  //bridge_two_avalon_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign bridge_two_avalon_slave_arb_share_counter_next_value = bridge_two_avalon_slave_firsttransfer ? (bridge_two_avalon_slave_arb_share_set_values - 1) : |bridge_two_avalon_slave_arb_share_counter ? (bridge_two_avalon_slave_arb_share_counter - 1) : 0;

  //bridge_two_avalon_slave_allgrants all slave grants, which is an e_mux
  assign bridge_two_avalon_slave_allgrants = |bridge_two_avalon_slave_grant_vector;

  //bridge_two_avalon_slave_end_xfer assignment, which is an e_assign
  assign bridge_two_avalon_slave_end_xfer = ~(bridge_two_avalon_slave_waits_for_read | bridge_two_avalon_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_bridge_two_avalon_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_bridge_two_avalon_slave = bridge_two_avalon_slave_end_xfer & (~bridge_two_avalon_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //bridge_two_avalon_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign bridge_two_avalon_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_bridge_two_avalon_slave & bridge_two_avalon_slave_allgrants) | (end_xfer_arb_share_counter_term_bridge_two_avalon_slave & ~bridge_two_avalon_slave_non_bursting_master_requests);

  //bridge_two_avalon_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bridge_two_avalon_slave_arb_share_counter <= 0;
      else if (bridge_two_avalon_slave_arb_counter_enable)
          bridge_two_avalon_slave_arb_share_counter <= bridge_two_avalon_slave_arb_share_counter_next_value;
    end


  //bridge_two_avalon_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bridge_two_avalon_slave_slavearbiterlockenable <= 0;
      else if ((|bridge_two_avalon_slave_master_qreq_vector & end_xfer_arb_share_counter_term_bridge_two_avalon_slave) | (end_xfer_arb_share_counter_term_bridge_two_avalon_slave & ~bridge_two_avalon_slave_non_bursting_master_requests))
          bridge_two_avalon_slave_slavearbiterlockenable <= |bridge_two_avalon_slave_arb_share_counter_next_value;
    end


  //cpu_two/data_master bridge_two/avalon_slave arbiterlock, which is an e_assign
  assign cpu_two_data_master_arbiterlock = bridge_two_avalon_slave_slavearbiterlockenable & cpu_two_data_master_continuerequest;

  //bridge_two_avalon_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign bridge_two_avalon_slave_slavearbiterlockenable2 = |bridge_two_avalon_slave_arb_share_counter_next_value;

  //cpu_two/data_master bridge_two/avalon_slave arbiterlock2, which is an e_assign
  assign cpu_two_data_master_arbiterlock2 = bridge_two_avalon_slave_slavearbiterlockenable2 & cpu_two_data_master_continuerequest;

  //bridge_two_avalon_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign bridge_two_avalon_slave_any_continuerequest = 1;

  //cpu_two_data_master_continuerequest continued request, which is an e_assign
  assign cpu_two_data_master_continuerequest = 1;

  assign cpu_two_data_master_qualified_request_bridge_two_avalon_slave = cpu_two_data_master_requests_bridge_two_avalon_slave & ~((cpu_two_data_master_read & ((|cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register))) | ((~cpu_two_data_master_waitrequest) & cpu_two_data_master_write));
  //cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register_in = cpu_two_data_master_granted_bridge_two_avalon_slave & cpu_two_data_master_read & ~bridge_two_avalon_slave_waits_for_read & ~(|cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register);

  //shift register p1 cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register = {cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register, cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register_in};

  //cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register <= 0;
      else 
        cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register <= p1_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register;
    end


  //local readdatavalid cpu_two_data_master_read_data_valid_bridge_two_avalon_slave, which is an e_mux
  assign cpu_two_data_master_read_data_valid_bridge_two_avalon_slave = cpu_two_data_master_read_data_valid_bridge_two_avalon_slave_shift_register;

  //bridge_two_avalon_slave_writedata mux, which is an e_mux
  assign bridge_two_avalon_slave_writedata = cpu_two_data_master_writedata;

  //master is always granted when requested
  assign cpu_two_data_master_granted_bridge_two_avalon_slave = cpu_two_data_master_qualified_request_bridge_two_avalon_slave;

  //cpu_two/data_master saved-grant bridge_two/avalon_slave, which is an e_assign
  assign cpu_two_data_master_saved_grant_bridge_two_avalon_slave = cpu_two_data_master_requests_bridge_two_avalon_slave;

  //allow new arb cycle for bridge_two/avalon_slave, which is an e_assign
  assign bridge_two_avalon_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign bridge_two_avalon_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign bridge_two_avalon_slave_master_qreq_vector = 1;

  //~bridge_two_avalon_slave_reset assignment, which is an e_assign
  assign bridge_two_avalon_slave_reset = ~reset_n;

  assign bridge_two_avalon_slave_chipselect = cpu_two_data_master_granted_bridge_two_avalon_slave;
  //bridge_two_avalon_slave_firsttransfer first transaction, which is an e_assign
  assign bridge_two_avalon_slave_firsttransfer = bridge_two_avalon_slave_begins_xfer ? bridge_two_avalon_slave_unreg_firsttransfer : bridge_two_avalon_slave_reg_firsttransfer;

  //bridge_two_avalon_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign bridge_two_avalon_slave_unreg_firsttransfer = ~(bridge_two_avalon_slave_slavearbiterlockenable & bridge_two_avalon_slave_any_continuerequest);

  //bridge_two_avalon_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          bridge_two_avalon_slave_reg_firsttransfer <= 1'b1;
      else if (bridge_two_avalon_slave_begins_xfer)
          bridge_two_avalon_slave_reg_firsttransfer <= bridge_two_avalon_slave_unreg_firsttransfer;
    end


  //bridge_two_avalon_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign bridge_two_avalon_slave_beginbursttransfer_internal = bridge_two_avalon_slave_begins_xfer;

  //bridge_two_avalon_slave_read assignment, which is an e_mux
  assign bridge_two_avalon_slave_read = cpu_two_data_master_granted_bridge_two_avalon_slave & cpu_two_data_master_read;

  //bridge_two_avalon_slave_write assignment, which is an e_mux
  assign bridge_two_avalon_slave_write = cpu_two_data_master_granted_bridge_two_avalon_slave & cpu_two_data_master_write;

  assign shifted_address_to_bridge_two_avalon_slave_from_cpu_two_data_master = cpu_two_data_master_address_to_slave;
  //bridge_two_avalon_slave_address mux, which is an e_mux
  assign bridge_two_avalon_slave_address = shifted_address_to_bridge_two_avalon_slave_from_cpu_two_data_master >> 2;

  //d1_bridge_two_avalon_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_bridge_two_avalon_slave_end_xfer <= 1;
      else 
        d1_bridge_two_avalon_slave_end_xfer <= bridge_two_avalon_slave_end_xfer;
    end


  //bridge_two_avalon_slave_waits_for_read in a cycle, which is an e_mux
  assign bridge_two_avalon_slave_waits_for_read = bridge_two_avalon_slave_in_a_read_cycle & bridge_two_avalon_slave_waitrequest_from_sa;

  //bridge_two_avalon_slave_in_a_read_cycle assignment, which is an e_assign
  assign bridge_two_avalon_slave_in_a_read_cycle = cpu_two_data_master_granted_bridge_two_avalon_slave & cpu_two_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = bridge_two_avalon_slave_in_a_read_cycle;

  //bridge_two_avalon_slave_waits_for_write in a cycle, which is an e_mux
  assign bridge_two_avalon_slave_waits_for_write = bridge_two_avalon_slave_in_a_write_cycle & bridge_two_avalon_slave_waitrequest_from_sa;

  //bridge_two_avalon_slave_in_a_write_cycle assignment, which is an e_assign
  assign bridge_two_avalon_slave_in_a_write_cycle = cpu_two_data_master_granted_bridge_two_avalon_slave & cpu_two_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = bridge_two_avalon_slave_in_a_write_cycle;

  assign wait_for_bridge_two_avalon_slave_counter = 0;
  //bridge_two_avalon_slave_byteenable byte enable port mux, which is an e_mux
  assign bridge_two_avalon_slave_byteenable = (cpu_two_data_master_granted_bridge_two_avalon_slave)? cpu_two_data_master_byteenable :
    -1;

  //assign bridge_two_avalon_slave_irq_from_sa = bridge_two_avalon_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign bridge_two_avalon_slave_irq_from_sa = bridge_two_avalon_slave_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //bridge_two/avalon_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_one_jtag_debug_module_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_one_data_master_address_to_slave,
                                               cpu_one_data_master_byteenable,
                                               cpu_one_data_master_debugaccess,
                                               cpu_one_data_master_read,
                                               cpu_one_data_master_waitrequest,
                                               cpu_one_data_master_write,
                                               cpu_one_data_master_writedata,
                                               cpu_one_instruction_master_address_to_slave,
                                               cpu_one_instruction_master_latency_counter,
                                               cpu_one_instruction_master_read,
                                               cpu_one_jtag_debug_module_readdata,
                                               cpu_one_jtag_debug_module_resetrequest,
                                               reset_n,

                                              // outputs:
                                               cpu_one_data_master_granted_cpu_one_jtag_debug_module,
                                               cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module,
                                               cpu_one_data_master_read_data_valid_cpu_one_jtag_debug_module,
                                               cpu_one_data_master_requests_cpu_one_jtag_debug_module,
                                               cpu_one_instruction_master_granted_cpu_one_jtag_debug_module,
                                               cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module,
                                               cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module,
                                               cpu_one_instruction_master_requests_cpu_one_jtag_debug_module,
                                               cpu_one_jtag_debug_module_address,
                                               cpu_one_jtag_debug_module_begintransfer,
                                               cpu_one_jtag_debug_module_byteenable,
                                               cpu_one_jtag_debug_module_chipselect,
                                               cpu_one_jtag_debug_module_debugaccess,
                                               cpu_one_jtag_debug_module_readdata_from_sa,
                                               cpu_one_jtag_debug_module_reset,
                                               cpu_one_jtag_debug_module_reset_n,
                                               cpu_one_jtag_debug_module_resetrequest_from_sa,
                                               cpu_one_jtag_debug_module_write,
                                               cpu_one_jtag_debug_module_writedata,
                                               d1_cpu_one_jtag_debug_module_end_xfer
                                            )
;

  output           cpu_one_data_master_granted_cpu_one_jtag_debug_module;
  output           cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module;
  output           cpu_one_data_master_read_data_valid_cpu_one_jtag_debug_module;
  output           cpu_one_data_master_requests_cpu_one_jtag_debug_module;
  output           cpu_one_instruction_master_granted_cpu_one_jtag_debug_module;
  output           cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module;
  output           cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module;
  output           cpu_one_instruction_master_requests_cpu_one_jtag_debug_module;
  output  [  8: 0] cpu_one_jtag_debug_module_address;
  output           cpu_one_jtag_debug_module_begintransfer;
  output  [  3: 0] cpu_one_jtag_debug_module_byteenable;
  output           cpu_one_jtag_debug_module_chipselect;
  output           cpu_one_jtag_debug_module_debugaccess;
  output  [ 31: 0] cpu_one_jtag_debug_module_readdata_from_sa;
  output           cpu_one_jtag_debug_module_reset;
  output           cpu_one_jtag_debug_module_reset_n;
  output           cpu_one_jtag_debug_module_resetrequest_from_sa;
  output           cpu_one_jtag_debug_module_write;
  output  [ 31: 0] cpu_one_jtag_debug_module_writedata;
  output           d1_cpu_one_jtag_debug_module_end_xfer;
  input            clk;
  input   [ 19: 0] cpu_one_data_master_address_to_slave;
  input   [  3: 0] cpu_one_data_master_byteenable;
  input            cpu_one_data_master_debugaccess;
  input            cpu_one_data_master_read;
  input            cpu_one_data_master_waitrequest;
  input            cpu_one_data_master_write;
  input   [ 31: 0] cpu_one_data_master_writedata;
  input   [ 19: 0] cpu_one_instruction_master_address_to_slave;
  input            cpu_one_instruction_master_latency_counter;
  input            cpu_one_instruction_master_read;
  input   [ 31: 0] cpu_one_jtag_debug_module_readdata;
  input            cpu_one_jtag_debug_module_resetrequest;
  input            reset_n;

  wire             cpu_one_data_master_arbiterlock;
  wire             cpu_one_data_master_arbiterlock2;
  wire             cpu_one_data_master_continuerequest;
  wire             cpu_one_data_master_granted_cpu_one_jtag_debug_module;
  wire             cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module;
  wire             cpu_one_data_master_read_data_valid_cpu_one_jtag_debug_module;
  wire             cpu_one_data_master_requests_cpu_one_jtag_debug_module;
  wire             cpu_one_data_master_saved_grant_cpu_one_jtag_debug_module;
  wire             cpu_one_instruction_master_arbiterlock;
  wire             cpu_one_instruction_master_arbiterlock2;
  wire             cpu_one_instruction_master_continuerequest;
  wire             cpu_one_instruction_master_granted_cpu_one_jtag_debug_module;
  wire             cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module;
  wire             cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module;
  wire             cpu_one_instruction_master_requests_cpu_one_jtag_debug_module;
  wire             cpu_one_instruction_master_saved_grant_cpu_one_jtag_debug_module;
  wire    [  8: 0] cpu_one_jtag_debug_module_address;
  wire             cpu_one_jtag_debug_module_allgrants;
  wire             cpu_one_jtag_debug_module_allow_new_arb_cycle;
  wire             cpu_one_jtag_debug_module_any_bursting_master_saved_grant;
  wire             cpu_one_jtag_debug_module_any_continuerequest;
  reg     [  1: 0] cpu_one_jtag_debug_module_arb_addend;
  wire             cpu_one_jtag_debug_module_arb_counter_enable;
  reg              cpu_one_jtag_debug_module_arb_share_counter;
  wire             cpu_one_jtag_debug_module_arb_share_counter_next_value;
  wire             cpu_one_jtag_debug_module_arb_share_set_values;
  wire    [  1: 0] cpu_one_jtag_debug_module_arb_winner;
  wire             cpu_one_jtag_debug_module_arbitration_holdoff_internal;
  wire             cpu_one_jtag_debug_module_beginbursttransfer_internal;
  wire             cpu_one_jtag_debug_module_begins_xfer;
  wire             cpu_one_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_one_jtag_debug_module_byteenable;
  wire             cpu_one_jtag_debug_module_chipselect;
  wire    [  3: 0] cpu_one_jtag_debug_module_chosen_master_double_vector;
  wire    [  1: 0] cpu_one_jtag_debug_module_chosen_master_rot_left;
  wire             cpu_one_jtag_debug_module_debugaccess;
  wire             cpu_one_jtag_debug_module_end_xfer;
  wire             cpu_one_jtag_debug_module_firsttransfer;
  wire    [  1: 0] cpu_one_jtag_debug_module_grant_vector;
  wire             cpu_one_jtag_debug_module_in_a_read_cycle;
  wire             cpu_one_jtag_debug_module_in_a_write_cycle;
  wire    [  1: 0] cpu_one_jtag_debug_module_master_qreq_vector;
  wire             cpu_one_jtag_debug_module_non_bursting_master_requests;
  wire    [ 31: 0] cpu_one_jtag_debug_module_readdata_from_sa;
  reg              cpu_one_jtag_debug_module_reg_firsttransfer;
  wire             cpu_one_jtag_debug_module_reset;
  wire             cpu_one_jtag_debug_module_reset_n;
  wire             cpu_one_jtag_debug_module_resetrequest_from_sa;
  reg     [  1: 0] cpu_one_jtag_debug_module_saved_chosen_master_vector;
  reg              cpu_one_jtag_debug_module_slavearbiterlockenable;
  wire             cpu_one_jtag_debug_module_slavearbiterlockenable2;
  wire             cpu_one_jtag_debug_module_unreg_firsttransfer;
  wire             cpu_one_jtag_debug_module_waits_for_read;
  wire             cpu_one_jtag_debug_module_waits_for_write;
  wire             cpu_one_jtag_debug_module_write;
  wire    [ 31: 0] cpu_one_jtag_debug_module_writedata;
  reg              d1_cpu_one_jtag_debug_module_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_cpu_one_jtag_debug_module;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_one_data_master_granted_slave_cpu_one_jtag_debug_module;
  reg              last_cycle_cpu_one_instruction_master_granted_slave_cpu_one_jtag_debug_module;
  wire    [ 19: 0] shifted_address_to_cpu_one_jtag_debug_module_from_cpu_one_data_master;
  wire    [ 19: 0] shifted_address_to_cpu_one_jtag_debug_module_from_cpu_one_instruction_master;
  wire             wait_for_cpu_one_jtag_debug_module_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~cpu_one_jtag_debug_module_end_xfer;
    end


  assign cpu_one_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module | cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module));
  //assign cpu_one_jtag_debug_module_readdata_from_sa = cpu_one_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_one_jtag_debug_module_readdata_from_sa = cpu_one_jtag_debug_module_readdata;

  assign cpu_one_data_master_requests_cpu_one_jtag_debug_module = ({cpu_one_data_master_address_to_slave[19 : 11] , 11'b0} == 20'h80000) & (cpu_one_data_master_read | cpu_one_data_master_write);
  //cpu_one_jtag_debug_module_arb_share_counter set values, which is an e_mux
  assign cpu_one_jtag_debug_module_arb_share_set_values = 1;

  //cpu_one_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
  assign cpu_one_jtag_debug_module_non_bursting_master_requests = cpu_one_data_master_requests_cpu_one_jtag_debug_module |
    cpu_one_instruction_master_requests_cpu_one_jtag_debug_module |
    cpu_one_data_master_requests_cpu_one_jtag_debug_module |
    cpu_one_instruction_master_requests_cpu_one_jtag_debug_module;

  //cpu_one_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
  assign cpu_one_jtag_debug_module_any_bursting_master_saved_grant = 0;

  //cpu_one_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
  assign cpu_one_jtag_debug_module_arb_share_counter_next_value = cpu_one_jtag_debug_module_firsttransfer ? (cpu_one_jtag_debug_module_arb_share_set_values - 1) : |cpu_one_jtag_debug_module_arb_share_counter ? (cpu_one_jtag_debug_module_arb_share_counter - 1) : 0;

  //cpu_one_jtag_debug_module_allgrants all slave grants, which is an e_mux
  assign cpu_one_jtag_debug_module_allgrants = (|cpu_one_jtag_debug_module_grant_vector) |
    (|cpu_one_jtag_debug_module_grant_vector) |
    (|cpu_one_jtag_debug_module_grant_vector) |
    (|cpu_one_jtag_debug_module_grant_vector);

  //cpu_one_jtag_debug_module_end_xfer assignment, which is an e_assign
  assign cpu_one_jtag_debug_module_end_xfer = ~(cpu_one_jtag_debug_module_waits_for_read | cpu_one_jtag_debug_module_waits_for_write);

  //end_xfer_arb_share_counter_term_cpu_one_jtag_debug_module arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_cpu_one_jtag_debug_module = cpu_one_jtag_debug_module_end_xfer & (~cpu_one_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //cpu_one_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
  assign cpu_one_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_one_jtag_debug_module & cpu_one_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_one_jtag_debug_module & ~cpu_one_jtag_debug_module_non_bursting_master_requests);

  //cpu_one_jtag_debug_module_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_jtag_debug_module_arb_share_counter <= 0;
      else if (cpu_one_jtag_debug_module_arb_counter_enable)
          cpu_one_jtag_debug_module_arb_share_counter <= cpu_one_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu_one_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_jtag_debug_module_slavearbiterlockenable <= 0;
      else if ((|cpu_one_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_one_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_one_jtag_debug_module & ~cpu_one_jtag_debug_module_non_bursting_master_requests))
          cpu_one_jtag_debug_module_slavearbiterlockenable <= |cpu_one_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu_one/data_master cpu_one/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_one_data_master_arbiterlock = cpu_one_jtag_debug_module_slavearbiterlockenable & cpu_one_data_master_continuerequest;

  //cpu_one_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign cpu_one_jtag_debug_module_slavearbiterlockenable2 = |cpu_one_jtag_debug_module_arb_share_counter_next_value;

  //cpu_one/data_master cpu_one/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_one_data_master_arbiterlock2 = cpu_one_jtag_debug_module_slavearbiterlockenable2 & cpu_one_data_master_continuerequest;

  //cpu_one/instruction_master cpu_one/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_one_instruction_master_arbiterlock = cpu_one_jtag_debug_module_slavearbiterlockenable & cpu_one_instruction_master_continuerequest;

  //cpu_one/instruction_master cpu_one/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_one_instruction_master_arbiterlock2 = cpu_one_jtag_debug_module_slavearbiterlockenable2 & cpu_one_instruction_master_continuerequest;

  //cpu_one/instruction_master granted cpu_one/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_one_instruction_master_granted_slave_cpu_one_jtag_debug_module <= 0;
      else 
        last_cycle_cpu_one_instruction_master_granted_slave_cpu_one_jtag_debug_module <= cpu_one_instruction_master_saved_grant_cpu_one_jtag_debug_module ? 1 : (cpu_one_jtag_debug_module_arbitration_holdoff_internal | ~cpu_one_instruction_master_requests_cpu_one_jtag_debug_module) ? 0 : last_cycle_cpu_one_instruction_master_granted_slave_cpu_one_jtag_debug_module;
    end


  //cpu_one_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_one_instruction_master_continuerequest = last_cycle_cpu_one_instruction_master_granted_slave_cpu_one_jtag_debug_module & cpu_one_instruction_master_requests_cpu_one_jtag_debug_module;

  //cpu_one_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
  assign cpu_one_jtag_debug_module_any_continuerequest = cpu_one_instruction_master_continuerequest |
    cpu_one_data_master_continuerequest;

  assign cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module = cpu_one_data_master_requests_cpu_one_jtag_debug_module & ~(((~cpu_one_data_master_waitrequest) & cpu_one_data_master_write) | cpu_one_instruction_master_arbiterlock);
  //cpu_one_jtag_debug_module_writedata mux, which is an e_mux
  assign cpu_one_jtag_debug_module_writedata = cpu_one_data_master_writedata;

  assign cpu_one_instruction_master_requests_cpu_one_jtag_debug_module = (({cpu_one_instruction_master_address_to_slave[19 : 11] , 11'b0} == 20'h80000) & (cpu_one_instruction_master_read)) & cpu_one_instruction_master_read;
  //cpu_one/data_master granted cpu_one/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_one_data_master_granted_slave_cpu_one_jtag_debug_module <= 0;
      else 
        last_cycle_cpu_one_data_master_granted_slave_cpu_one_jtag_debug_module <= cpu_one_data_master_saved_grant_cpu_one_jtag_debug_module ? 1 : (cpu_one_jtag_debug_module_arbitration_holdoff_internal | ~cpu_one_data_master_requests_cpu_one_jtag_debug_module) ? 0 : last_cycle_cpu_one_data_master_granted_slave_cpu_one_jtag_debug_module;
    end


  //cpu_one_data_master_continuerequest continued request, which is an e_mux
  assign cpu_one_data_master_continuerequest = last_cycle_cpu_one_data_master_granted_slave_cpu_one_jtag_debug_module & cpu_one_data_master_requests_cpu_one_jtag_debug_module;

  assign cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module = cpu_one_instruction_master_requests_cpu_one_jtag_debug_module & ~((cpu_one_instruction_master_read & ((cpu_one_instruction_master_latency_counter != 0))) | cpu_one_data_master_arbiterlock);
  //local readdatavalid cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module, which is an e_mux
  assign cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module = cpu_one_instruction_master_granted_cpu_one_jtag_debug_module & cpu_one_instruction_master_read & ~cpu_one_jtag_debug_module_waits_for_read;

  //allow new arb cycle for cpu_one/jtag_debug_module, which is an e_assign
  assign cpu_one_jtag_debug_module_allow_new_arb_cycle = ~cpu_one_data_master_arbiterlock & ~cpu_one_instruction_master_arbiterlock;

  //cpu_one/instruction_master assignment into master qualified-requests vector for cpu_one/jtag_debug_module, which is an e_assign
  assign cpu_one_jtag_debug_module_master_qreq_vector[0] = cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module;

  //cpu_one/instruction_master grant cpu_one/jtag_debug_module, which is an e_assign
  assign cpu_one_instruction_master_granted_cpu_one_jtag_debug_module = cpu_one_jtag_debug_module_grant_vector[0];

  //cpu_one/instruction_master saved-grant cpu_one/jtag_debug_module, which is an e_assign
  assign cpu_one_instruction_master_saved_grant_cpu_one_jtag_debug_module = cpu_one_jtag_debug_module_arb_winner[0] && cpu_one_instruction_master_requests_cpu_one_jtag_debug_module;

  //cpu_one/data_master assignment into master qualified-requests vector for cpu_one/jtag_debug_module, which is an e_assign
  assign cpu_one_jtag_debug_module_master_qreq_vector[1] = cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module;

  //cpu_one/data_master grant cpu_one/jtag_debug_module, which is an e_assign
  assign cpu_one_data_master_granted_cpu_one_jtag_debug_module = cpu_one_jtag_debug_module_grant_vector[1];

  //cpu_one/data_master saved-grant cpu_one/jtag_debug_module, which is an e_assign
  assign cpu_one_data_master_saved_grant_cpu_one_jtag_debug_module = cpu_one_jtag_debug_module_arb_winner[1] && cpu_one_data_master_requests_cpu_one_jtag_debug_module;

  //cpu_one/jtag_debug_module chosen-master double-vector, which is an e_assign
  assign cpu_one_jtag_debug_module_chosen_master_double_vector = {cpu_one_jtag_debug_module_master_qreq_vector, cpu_one_jtag_debug_module_master_qreq_vector} & ({~cpu_one_jtag_debug_module_master_qreq_vector, ~cpu_one_jtag_debug_module_master_qreq_vector} + cpu_one_jtag_debug_module_arb_addend);

  //stable onehot encoding of arb winner
  assign cpu_one_jtag_debug_module_arb_winner = (cpu_one_jtag_debug_module_allow_new_arb_cycle & | cpu_one_jtag_debug_module_grant_vector) ? cpu_one_jtag_debug_module_grant_vector : cpu_one_jtag_debug_module_saved_chosen_master_vector;

  //saved cpu_one_jtag_debug_module_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_jtag_debug_module_saved_chosen_master_vector <= 0;
      else if (cpu_one_jtag_debug_module_allow_new_arb_cycle)
          cpu_one_jtag_debug_module_saved_chosen_master_vector <= |cpu_one_jtag_debug_module_grant_vector ? cpu_one_jtag_debug_module_grant_vector : cpu_one_jtag_debug_module_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign cpu_one_jtag_debug_module_grant_vector = {(cpu_one_jtag_debug_module_chosen_master_double_vector[1] | cpu_one_jtag_debug_module_chosen_master_double_vector[3]),
    (cpu_one_jtag_debug_module_chosen_master_double_vector[0] | cpu_one_jtag_debug_module_chosen_master_double_vector[2])};

  //cpu_one/jtag_debug_module chosen master rotated left, which is an e_assign
  assign cpu_one_jtag_debug_module_chosen_master_rot_left = (cpu_one_jtag_debug_module_arb_winner << 1) ? (cpu_one_jtag_debug_module_arb_winner << 1) : 1;

  //cpu_one/jtag_debug_module's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_jtag_debug_module_arb_addend <= 1;
      else if (|cpu_one_jtag_debug_module_grant_vector)
          cpu_one_jtag_debug_module_arb_addend <= cpu_one_jtag_debug_module_end_xfer? cpu_one_jtag_debug_module_chosen_master_rot_left : cpu_one_jtag_debug_module_grant_vector;
    end


  assign cpu_one_jtag_debug_module_begintransfer = cpu_one_jtag_debug_module_begins_xfer;
  //assign lhs ~cpu_one_jtag_debug_module_reset of type reset_n to cpu_one_jtag_debug_module_reset_n, which is an e_assign
  assign cpu_one_jtag_debug_module_reset = ~cpu_one_jtag_debug_module_reset_n;

  //cpu_one_jtag_debug_module_reset_n assignment, which is an e_assign
  assign cpu_one_jtag_debug_module_reset_n = reset_n;

  //assign cpu_one_jtag_debug_module_resetrequest_from_sa = cpu_one_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_one_jtag_debug_module_resetrequest_from_sa = cpu_one_jtag_debug_module_resetrequest;

  assign cpu_one_jtag_debug_module_chipselect = cpu_one_data_master_granted_cpu_one_jtag_debug_module | cpu_one_instruction_master_granted_cpu_one_jtag_debug_module;
  //cpu_one_jtag_debug_module_firsttransfer first transaction, which is an e_assign
  assign cpu_one_jtag_debug_module_firsttransfer = cpu_one_jtag_debug_module_begins_xfer ? cpu_one_jtag_debug_module_unreg_firsttransfer : cpu_one_jtag_debug_module_reg_firsttransfer;

  //cpu_one_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign
  assign cpu_one_jtag_debug_module_unreg_firsttransfer = ~(cpu_one_jtag_debug_module_slavearbiterlockenable & cpu_one_jtag_debug_module_any_continuerequest);

  //cpu_one_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_jtag_debug_module_reg_firsttransfer <= 1'b1;
      else if (cpu_one_jtag_debug_module_begins_xfer)
          cpu_one_jtag_debug_module_reg_firsttransfer <= cpu_one_jtag_debug_module_unreg_firsttransfer;
    end


  //cpu_one_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cpu_one_jtag_debug_module_beginbursttransfer_internal = cpu_one_jtag_debug_module_begins_xfer;

  //cpu_one_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cpu_one_jtag_debug_module_arbitration_holdoff_internal = cpu_one_jtag_debug_module_begins_xfer & cpu_one_jtag_debug_module_firsttransfer;

  //cpu_one_jtag_debug_module_write assignment, which is an e_mux
  assign cpu_one_jtag_debug_module_write = cpu_one_data_master_granted_cpu_one_jtag_debug_module & cpu_one_data_master_write;

  assign shifted_address_to_cpu_one_jtag_debug_module_from_cpu_one_data_master = cpu_one_data_master_address_to_slave;
  //cpu_one_jtag_debug_module_address mux, which is an e_mux
  assign cpu_one_jtag_debug_module_address = (cpu_one_data_master_granted_cpu_one_jtag_debug_module)? (shifted_address_to_cpu_one_jtag_debug_module_from_cpu_one_data_master >> 2) :
    (shifted_address_to_cpu_one_jtag_debug_module_from_cpu_one_instruction_master >> 2);

  assign shifted_address_to_cpu_one_jtag_debug_module_from_cpu_one_instruction_master = cpu_one_instruction_master_address_to_slave;
  //d1_cpu_one_jtag_debug_module_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cpu_one_jtag_debug_module_end_xfer <= 1;
      else 
        d1_cpu_one_jtag_debug_module_end_xfer <= cpu_one_jtag_debug_module_end_xfer;
    end


  //cpu_one_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  assign cpu_one_jtag_debug_module_waits_for_read = cpu_one_jtag_debug_module_in_a_read_cycle & cpu_one_jtag_debug_module_begins_xfer;

  //cpu_one_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  assign cpu_one_jtag_debug_module_in_a_read_cycle = (cpu_one_data_master_granted_cpu_one_jtag_debug_module & cpu_one_data_master_read) | (cpu_one_instruction_master_granted_cpu_one_jtag_debug_module & cpu_one_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cpu_one_jtag_debug_module_in_a_read_cycle;

  //cpu_one_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  assign cpu_one_jtag_debug_module_waits_for_write = cpu_one_jtag_debug_module_in_a_write_cycle & 0;

  //cpu_one_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  assign cpu_one_jtag_debug_module_in_a_write_cycle = cpu_one_data_master_granted_cpu_one_jtag_debug_module & cpu_one_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cpu_one_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu_one_jtag_debug_module_counter = 0;
  //cpu_one_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  assign cpu_one_jtag_debug_module_byteenable = (cpu_one_data_master_granted_cpu_one_jtag_debug_module)? cpu_one_data_master_byteenable :
    -1;

  //debugaccess mux, which is an e_mux
  assign cpu_one_jtag_debug_module_debugaccess = (cpu_one_data_master_granted_cpu_one_jtag_debug_module)? cpu_one_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_one/jtag_debug_module enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_one_data_master_granted_cpu_one_jtag_debug_module + cpu_one_instruction_master_granted_cpu_one_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_one_data_master_saved_grant_cpu_one_jtag_debug_module + cpu_one_instruction_master_saved_grant_cpu_one_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_one_data_master_arbitrator (
                                        // inputs:
                                         bridge_one_avalon_slave_irq_from_sa,
                                         bridge_one_avalon_slave_readdata_from_sa,
                                         bridge_one_avalon_slave_waitrequest_from_sa,
                                         bridge_two_avalon_slave_irq_from_sa,
                                         clk,
                                         cpu_one_data_master_address,
                                         cpu_one_data_master_granted_bridge_one_avalon_slave,
                                         cpu_one_data_master_granted_cpu_one_jtag_debug_module,
                                         cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave,
                                         cpu_one_data_master_granted_onchip_mem_one_s1,
                                         cpu_one_data_master_qualified_request_bridge_one_avalon_slave,
                                         cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module,
                                         cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave,
                                         cpu_one_data_master_qualified_request_onchip_mem_one_s1,
                                         cpu_one_data_master_read,
                                         cpu_one_data_master_read_data_valid_bridge_one_avalon_slave,
                                         cpu_one_data_master_read_data_valid_cpu_one_jtag_debug_module,
                                         cpu_one_data_master_read_data_valid_jtag_uart_one_avalon_jtag_slave,
                                         cpu_one_data_master_read_data_valid_onchip_mem_one_s1,
                                         cpu_one_data_master_requests_bridge_one_avalon_slave,
                                         cpu_one_data_master_requests_cpu_one_jtag_debug_module,
                                         cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave,
                                         cpu_one_data_master_requests_onchip_mem_one_s1,
                                         cpu_one_data_master_write,
                                         cpu_one_jtag_debug_module_readdata_from_sa,
                                         d1_bridge_one_avalon_slave_end_xfer,
                                         d1_cpu_one_jtag_debug_module_end_xfer,
                                         d1_jtag_uart_one_avalon_jtag_slave_end_xfer,
                                         d1_onchip_mem_one_s1_end_xfer,
                                         jtag_uart_one_avalon_jtag_slave_irq_from_sa,
                                         jtag_uart_one_avalon_jtag_slave_readdata_from_sa,
                                         jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa,
                                         jtag_uart_two_avalon_jtag_slave_irq_from_sa,
                                         onchip_mem_one_s1_readdata_from_sa,
                                         registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave,
                                         registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1,
                                         reset_n,

                                        // outputs:
                                         cpu_one_data_master_address_to_slave,
                                         cpu_one_data_master_irq,
                                         cpu_one_data_master_readdata,
                                         cpu_one_data_master_waitrequest
                                      )
;

  output  [ 19: 0] cpu_one_data_master_address_to_slave;
  output  [ 31: 0] cpu_one_data_master_irq;
  output  [ 31: 0] cpu_one_data_master_readdata;
  output           cpu_one_data_master_waitrequest;
  input            bridge_one_avalon_slave_irq_from_sa;
  input   [ 31: 0] bridge_one_avalon_slave_readdata_from_sa;
  input            bridge_one_avalon_slave_waitrequest_from_sa;
  input            bridge_two_avalon_slave_irq_from_sa;
  input            clk;
  input   [ 19: 0] cpu_one_data_master_address;
  input            cpu_one_data_master_granted_bridge_one_avalon_slave;
  input            cpu_one_data_master_granted_cpu_one_jtag_debug_module;
  input            cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave;
  input            cpu_one_data_master_granted_onchip_mem_one_s1;
  input            cpu_one_data_master_qualified_request_bridge_one_avalon_slave;
  input            cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module;
  input            cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave;
  input            cpu_one_data_master_qualified_request_onchip_mem_one_s1;
  input            cpu_one_data_master_read;
  input            cpu_one_data_master_read_data_valid_bridge_one_avalon_slave;
  input            cpu_one_data_master_read_data_valid_cpu_one_jtag_debug_module;
  input            cpu_one_data_master_read_data_valid_jtag_uart_one_avalon_jtag_slave;
  input            cpu_one_data_master_read_data_valid_onchip_mem_one_s1;
  input            cpu_one_data_master_requests_bridge_one_avalon_slave;
  input            cpu_one_data_master_requests_cpu_one_jtag_debug_module;
  input            cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave;
  input            cpu_one_data_master_requests_onchip_mem_one_s1;
  input            cpu_one_data_master_write;
  input   [ 31: 0] cpu_one_jtag_debug_module_readdata_from_sa;
  input            d1_bridge_one_avalon_slave_end_xfer;
  input            d1_cpu_one_jtag_debug_module_end_xfer;
  input            d1_jtag_uart_one_avalon_jtag_slave_end_xfer;
  input            d1_onchip_mem_one_s1_end_xfer;
  input            jtag_uart_one_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] jtag_uart_one_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa;
  input            jtag_uart_two_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] onchip_mem_one_s1_readdata_from_sa;
  input            registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave;
  input            registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1;
  input            reset_n;

  wire    [ 19: 0] cpu_one_data_master_address_to_slave;
  wire    [ 31: 0] cpu_one_data_master_irq;
  wire    [ 31: 0] cpu_one_data_master_readdata;
  wire             cpu_one_data_master_run;
  reg              cpu_one_data_master_waitrequest;
  wire    [ 31: 0] p1_registered_cpu_one_data_master_readdata;
  wire             r_0;
  reg     [ 31: 0] registered_cpu_one_data_master_readdata;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_one_data_master_qualified_request_bridge_one_avalon_slave | registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave | ~cpu_one_data_master_requests_bridge_one_avalon_slave) & ((~cpu_one_data_master_qualified_request_bridge_one_avalon_slave | ~cpu_one_data_master_read | (registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave & cpu_one_data_master_read))) & ((~cpu_one_data_master_qualified_request_bridge_one_avalon_slave | ~(cpu_one_data_master_read | cpu_one_data_master_write) | (1 & ~bridge_one_avalon_slave_waitrequest_from_sa & (cpu_one_data_master_read | cpu_one_data_master_write)))) & 1 & (cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module | ~cpu_one_data_master_requests_cpu_one_jtag_debug_module) & (cpu_one_data_master_granted_cpu_one_jtag_debug_module | ~cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module) & ((~cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module | ~cpu_one_data_master_read | (1 & 1 & cpu_one_data_master_read))) & ((~cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module | ~cpu_one_data_master_write | (1 & cpu_one_data_master_write))) & 1 & (cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave | ~cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave) & ((~cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave | ~(cpu_one_data_master_read | cpu_one_data_master_write) | (1 & ~jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa & (cpu_one_data_master_read | cpu_one_data_master_write)))) & ((~cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave | ~(cpu_one_data_master_read | cpu_one_data_master_write) | (1 & ~jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa & (cpu_one_data_master_read | cpu_one_data_master_write)))) & 1 & (cpu_one_data_master_qualified_request_onchip_mem_one_s1 | registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1 | ~cpu_one_data_master_requests_onchip_mem_one_s1) & (cpu_one_data_master_granted_onchip_mem_one_s1 | ~cpu_one_data_master_qualified_request_onchip_mem_one_s1) & ((~cpu_one_data_master_qualified_request_onchip_mem_one_s1 | ~cpu_one_data_master_read | (registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1 & cpu_one_data_master_read))) & ((~cpu_one_data_master_qualified_request_onchip_mem_one_s1 | ~(cpu_one_data_master_read | cpu_one_data_master_write) | (1 & (cpu_one_data_master_read | cpu_one_data_master_write))));

  //cascaded wait assignment, which is an e_assign
  assign cpu_one_data_master_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_one_data_master_address_to_slave = cpu_one_data_master_address[19 : 0];

  //cpu_one/data_master readdata mux, which is an e_mux
  assign cpu_one_data_master_readdata = ({32 {~cpu_one_data_master_requests_bridge_one_avalon_slave}} | bridge_one_avalon_slave_readdata_from_sa) &
    ({32 {~cpu_one_data_master_requests_cpu_one_jtag_debug_module}} | cpu_one_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave}} | registered_cpu_one_data_master_readdata) &
    ({32 {~cpu_one_data_master_requests_onchip_mem_one_s1}} | onchip_mem_one_s1_readdata_from_sa);

  //actual waitrequest port, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_data_master_waitrequest <= ~0;
      else 
        cpu_one_data_master_waitrequest <= ~((~(cpu_one_data_master_read | cpu_one_data_master_write))? 0: (cpu_one_data_master_run & cpu_one_data_master_waitrequest));
    end


  //irq assign, which is an e_assign
  assign cpu_one_data_master_irq = {1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    bridge_two_avalon_slave_irq_from_sa,
    jtag_uart_two_avalon_jtag_slave_irq_from_sa,
    bridge_one_avalon_slave_irq_from_sa,
    jtag_uart_one_avalon_jtag_slave_irq_from_sa};

  //unpredictable registered wait state incoming data, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          registered_cpu_one_data_master_readdata <= 0;
      else 
        registered_cpu_one_data_master_readdata <= p1_registered_cpu_one_data_master_readdata;
    end


  //registered readdata mux, which is an e_mux
  assign p1_registered_cpu_one_data_master_readdata = {32 {~cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave}} | jtag_uart_one_avalon_jtag_slave_readdata_from_sa;


endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_one_instruction_master_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_one_instruction_master_address,
                                                cpu_one_instruction_master_granted_cpu_one_jtag_debug_module,
                                                cpu_one_instruction_master_granted_onchip_mem_one_s1,
                                                cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module,
                                                cpu_one_instruction_master_qualified_request_onchip_mem_one_s1,
                                                cpu_one_instruction_master_read,
                                                cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module,
                                                cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1,
                                                cpu_one_instruction_master_requests_cpu_one_jtag_debug_module,
                                                cpu_one_instruction_master_requests_onchip_mem_one_s1,
                                                cpu_one_jtag_debug_module_readdata_from_sa,
                                                d1_cpu_one_jtag_debug_module_end_xfer,
                                                d1_onchip_mem_one_s1_end_xfer,
                                                onchip_mem_one_s1_readdata_from_sa,
                                                reset_n,

                                               // outputs:
                                                cpu_one_instruction_master_address_to_slave,
                                                cpu_one_instruction_master_latency_counter,
                                                cpu_one_instruction_master_readdata,
                                                cpu_one_instruction_master_readdatavalid,
                                                cpu_one_instruction_master_waitrequest
                                             )
;

  output  [ 19: 0] cpu_one_instruction_master_address_to_slave;
  output           cpu_one_instruction_master_latency_counter;
  output  [ 31: 0] cpu_one_instruction_master_readdata;
  output           cpu_one_instruction_master_readdatavalid;
  output           cpu_one_instruction_master_waitrequest;
  input            clk;
  input   [ 19: 0] cpu_one_instruction_master_address;
  input            cpu_one_instruction_master_granted_cpu_one_jtag_debug_module;
  input            cpu_one_instruction_master_granted_onchip_mem_one_s1;
  input            cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module;
  input            cpu_one_instruction_master_qualified_request_onchip_mem_one_s1;
  input            cpu_one_instruction_master_read;
  input            cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module;
  input            cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1;
  input            cpu_one_instruction_master_requests_cpu_one_jtag_debug_module;
  input            cpu_one_instruction_master_requests_onchip_mem_one_s1;
  input   [ 31: 0] cpu_one_jtag_debug_module_readdata_from_sa;
  input            d1_cpu_one_jtag_debug_module_end_xfer;
  input            d1_onchip_mem_one_s1_end_xfer;
  input   [ 31: 0] onchip_mem_one_s1_readdata_from_sa;
  input            reset_n;

  reg              active_and_waiting_last_time;
  reg     [ 19: 0] cpu_one_instruction_master_address_last_time;
  wire    [ 19: 0] cpu_one_instruction_master_address_to_slave;
  wire             cpu_one_instruction_master_is_granted_some_slave;
  reg              cpu_one_instruction_master_latency_counter;
  reg              cpu_one_instruction_master_read_but_no_slave_selected;
  reg              cpu_one_instruction_master_read_last_time;
  wire    [ 31: 0] cpu_one_instruction_master_readdata;
  wire             cpu_one_instruction_master_readdatavalid;
  wire             cpu_one_instruction_master_run;
  wire             cpu_one_instruction_master_waitrequest;
  wire             latency_load_value;
  wire             p1_cpu_one_instruction_master_latency_counter;
  wire             pre_flush_cpu_one_instruction_master_readdatavalid;
  wire             r_0;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module | ~cpu_one_instruction_master_requests_cpu_one_jtag_debug_module) & (cpu_one_instruction_master_granted_cpu_one_jtag_debug_module | ~cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module) & ((~cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module | ~cpu_one_instruction_master_read | (1 & ~d1_cpu_one_jtag_debug_module_end_xfer & cpu_one_instruction_master_read))) & 1 & (cpu_one_instruction_master_qualified_request_onchip_mem_one_s1 | ~cpu_one_instruction_master_requests_onchip_mem_one_s1) & (cpu_one_instruction_master_granted_onchip_mem_one_s1 | ~cpu_one_instruction_master_qualified_request_onchip_mem_one_s1) & ((~cpu_one_instruction_master_qualified_request_onchip_mem_one_s1 | ~cpu_one_instruction_master_read | (1 & cpu_one_instruction_master_read)));

  //cascaded wait assignment, which is an e_assign
  assign cpu_one_instruction_master_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_one_instruction_master_address_to_slave = {5'b10000,
    cpu_one_instruction_master_address[14],
    2'b0,
    cpu_one_instruction_master_address[11 : 0]};

  //cpu_one_instruction_master_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_instruction_master_read_but_no_slave_selected <= 0;
      else 
        cpu_one_instruction_master_read_but_no_slave_selected <= cpu_one_instruction_master_read & cpu_one_instruction_master_run & ~cpu_one_instruction_master_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign cpu_one_instruction_master_is_granted_some_slave = cpu_one_instruction_master_granted_cpu_one_jtag_debug_module |
    cpu_one_instruction_master_granted_onchip_mem_one_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_cpu_one_instruction_master_readdatavalid = cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign cpu_one_instruction_master_readdatavalid = cpu_one_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_one_instruction_master_readdatavalid |
    cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module |
    cpu_one_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_one_instruction_master_readdatavalid;

  //cpu_one/instruction_master readdata mux, which is an e_mux
  assign cpu_one_instruction_master_readdata = ({32 {~(cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module & cpu_one_instruction_master_read)}} | cpu_one_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1}} | onchip_mem_one_s1_readdata_from_sa);

  //actual waitrequest port, which is an e_assign
  assign cpu_one_instruction_master_waitrequest = ~cpu_one_instruction_master_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_instruction_master_latency_counter <= 0;
      else 
        cpu_one_instruction_master_latency_counter <= p1_cpu_one_instruction_master_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_cpu_one_instruction_master_latency_counter = ((cpu_one_instruction_master_run & cpu_one_instruction_master_read))? latency_load_value :
    (cpu_one_instruction_master_latency_counter)? cpu_one_instruction_master_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = {1 {cpu_one_instruction_master_requests_onchip_mem_one_s1}} & 1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_one_instruction_master_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_instruction_master_address_last_time <= 0;
      else 
        cpu_one_instruction_master_address_last_time <= cpu_one_instruction_master_address;
    end


  //cpu_one/instruction_master waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= cpu_one_instruction_master_waitrequest & (cpu_one_instruction_master_read);
    end


  //cpu_one_instruction_master_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_one_instruction_master_address != cpu_one_instruction_master_address_last_time))
        begin
          $write("%0d ns: cpu_one_instruction_master_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_one_instruction_master_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_instruction_master_read_last_time <= 0;
      else 
        cpu_one_instruction_master_read_last_time <= cpu_one_instruction_master_read;
    end


  //cpu_one_instruction_master_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_one_instruction_master_read != cpu_one_instruction_master_read_last_time))
        begin
          $write("%0d ns: cpu_one_instruction_master_read did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_two_jtag_debug_module_arbitrator (
                                              // inputs:
                                               clk,
                                               cpu_two_data_master_address_to_slave,
                                               cpu_two_data_master_byteenable,
                                               cpu_two_data_master_debugaccess,
                                               cpu_two_data_master_read,
                                               cpu_two_data_master_waitrequest,
                                               cpu_two_data_master_write,
                                               cpu_two_data_master_writedata,
                                               cpu_two_instruction_master_address_to_slave,
                                               cpu_two_instruction_master_latency_counter,
                                               cpu_two_instruction_master_read,
                                               cpu_two_jtag_debug_module_readdata,
                                               cpu_two_jtag_debug_module_resetrequest,
                                               reset_n,

                                              // outputs:
                                               cpu_two_data_master_granted_cpu_two_jtag_debug_module,
                                               cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module,
                                               cpu_two_data_master_read_data_valid_cpu_two_jtag_debug_module,
                                               cpu_two_data_master_requests_cpu_two_jtag_debug_module,
                                               cpu_two_instruction_master_granted_cpu_two_jtag_debug_module,
                                               cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module,
                                               cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module,
                                               cpu_two_instruction_master_requests_cpu_two_jtag_debug_module,
                                               cpu_two_jtag_debug_module_address,
                                               cpu_two_jtag_debug_module_begintransfer,
                                               cpu_two_jtag_debug_module_byteenable,
                                               cpu_two_jtag_debug_module_chipselect,
                                               cpu_two_jtag_debug_module_debugaccess,
                                               cpu_two_jtag_debug_module_readdata_from_sa,
                                               cpu_two_jtag_debug_module_reset,
                                               cpu_two_jtag_debug_module_reset_n,
                                               cpu_two_jtag_debug_module_resetrequest_from_sa,
                                               cpu_two_jtag_debug_module_write,
                                               cpu_two_jtag_debug_module_writedata,
                                               d1_cpu_two_jtag_debug_module_end_xfer
                                            )
;

  output           cpu_two_data_master_granted_cpu_two_jtag_debug_module;
  output           cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module;
  output           cpu_two_data_master_read_data_valid_cpu_two_jtag_debug_module;
  output           cpu_two_data_master_requests_cpu_two_jtag_debug_module;
  output           cpu_two_instruction_master_granted_cpu_two_jtag_debug_module;
  output           cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module;
  output           cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module;
  output           cpu_two_instruction_master_requests_cpu_two_jtag_debug_module;
  output  [  8: 0] cpu_two_jtag_debug_module_address;
  output           cpu_two_jtag_debug_module_begintransfer;
  output  [  3: 0] cpu_two_jtag_debug_module_byteenable;
  output           cpu_two_jtag_debug_module_chipselect;
  output           cpu_two_jtag_debug_module_debugaccess;
  output  [ 31: 0] cpu_two_jtag_debug_module_readdata_from_sa;
  output           cpu_two_jtag_debug_module_reset;
  output           cpu_two_jtag_debug_module_reset_n;
  output           cpu_two_jtag_debug_module_resetrequest_from_sa;
  output           cpu_two_jtag_debug_module_write;
  output  [ 31: 0] cpu_two_jtag_debug_module_writedata;
  output           d1_cpu_two_jtag_debug_module_end_xfer;
  input            clk;
  input   [ 19: 0] cpu_two_data_master_address_to_slave;
  input   [  3: 0] cpu_two_data_master_byteenable;
  input            cpu_two_data_master_debugaccess;
  input            cpu_two_data_master_read;
  input            cpu_two_data_master_waitrequest;
  input            cpu_two_data_master_write;
  input   [ 31: 0] cpu_two_data_master_writedata;
  input   [ 19: 0] cpu_two_instruction_master_address_to_slave;
  input            cpu_two_instruction_master_latency_counter;
  input            cpu_two_instruction_master_read;
  input   [ 31: 0] cpu_two_jtag_debug_module_readdata;
  input            cpu_two_jtag_debug_module_resetrequest;
  input            reset_n;

  wire             cpu_two_data_master_arbiterlock;
  wire             cpu_two_data_master_arbiterlock2;
  wire             cpu_two_data_master_continuerequest;
  wire             cpu_two_data_master_granted_cpu_two_jtag_debug_module;
  wire             cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module;
  wire             cpu_two_data_master_read_data_valid_cpu_two_jtag_debug_module;
  wire             cpu_two_data_master_requests_cpu_two_jtag_debug_module;
  wire             cpu_two_data_master_saved_grant_cpu_two_jtag_debug_module;
  wire             cpu_two_instruction_master_arbiterlock;
  wire             cpu_two_instruction_master_arbiterlock2;
  wire             cpu_two_instruction_master_continuerequest;
  wire             cpu_two_instruction_master_granted_cpu_two_jtag_debug_module;
  wire             cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module;
  wire             cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module;
  wire             cpu_two_instruction_master_requests_cpu_two_jtag_debug_module;
  wire             cpu_two_instruction_master_saved_grant_cpu_two_jtag_debug_module;
  wire    [  8: 0] cpu_two_jtag_debug_module_address;
  wire             cpu_two_jtag_debug_module_allgrants;
  wire             cpu_two_jtag_debug_module_allow_new_arb_cycle;
  wire             cpu_two_jtag_debug_module_any_bursting_master_saved_grant;
  wire             cpu_two_jtag_debug_module_any_continuerequest;
  reg     [  1: 0] cpu_two_jtag_debug_module_arb_addend;
  wire             cpu_two_jtag_debug_module_arb_counter_enable;
  reg              cpu_two_jtag_debug_module_arb_share_counter;
  wire             cpu_two_jtag_debug_module_arb_share_counter_next_value;
  wire             cpu_two_jtag_debug_module_arb_share_set_values;
  wire    [  1: 0] cpu_two_jtag_debug_module_arb_winner;
  wire             cpu_two_jtag_debug_module_arbitration_holdoff_internal;
  wire             cpu_two_jtag_debug_module_beginbursttransfer_internal;
  wire             cpu_two_jtag_debug_module_begins_xfer;
  wire             cpu_two_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_two_jtag_debug_module_byteenable;
  wire             cpu_two_jtag_debug_module_chipselect;
  wire    [  3: 0] cpu_two_jtag_debug_module_chosen_master_double_vector;
  wire    [  1: 0] cpu_two_jtag_debug_module_chosen_master_rot_left;
  wire             cpu_two_jtag_debug_module_debugaccess;
  wire             cpu_two_jtag_debug_module_end_xfer;
  wire             cpu_two_jtag_debug_module_firsttransfer;
  wire    [  1: 0] cpu_two_jtag_debug_module_grant_vector;
  wire             cpu_two_jtag_debug_module_in_a_read_cycle;
  wire             cpu_two_jtag_debug_module_in_a_write_cycle;
  wire    [  1: 0] cpu_two_jtag_debug_module_master_qreq_vector;
  wire             cpu_two_jtag_debug_module_non_bursting_master_requests;
  wire    [ 31: 0] cpu_two_jtag_debug_module_readdata_from_sa;
  reg              cpu_two_jtag_debug_module_reg_firsttransfer;
  wire             cpu_two_jtag_debug_module_reset;
  wire             cpu_two_jtag_debug_module_reset_n;
  wire             cpu_two_jtag_debug_module_resetrequest_from_sa;
  reg     [  1: 0] cpu_two_jtag_debug_module_saved_chosen_master_vector;
  reg              cpu_two_jtag_debug_module_slavearbiterlockenable;
  wire             cpu_two_jtag_debug_module_slavearbiterlockenable2;
  wire             cpu_two_jtag_debug_module_unreg_firsttransfer;
  wire             cpu_two_jtag_debug_module_waits_for_read;
  wire             cpu_two_jtag_debug_module_waits_for_write;
  wire             cpu_two_jtag_debug_module_write;
  wire    [ 31: 0] cpu_two_jtag_debug_module_writedata;
  reg              d1_cpu_two_jtag_debug_module_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_cpu_two_jtag_debug_module;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_two_data_master_granted_slave_cpu_two_jtag_debug_module;
  reg              last_cycle_cpu_two_instruction_master_granted_slave_cpu_two_jtag_debug_module;
  wire    [ 19: 0] shifted_address_to_cpu_two_jtag_debug_module_from_cpu_two_data_master;
  wire    [ 19: 0] shifted_address_to_cpu_two_jtag_debug_module_from_cpu_two_instruction_master;
  wire             wait_for_cpu_two_jtag_debug_module_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~cpu_two_jtag_debug_module_end_xfer;
    end


  assign cpu_two_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module | cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module));
  //assign cpu_two_jtag_debug_module_readdata_from_sa = cpu_two_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_two_jtag_debug_module_readdata_from_sa = cpu_two_jtag_debug_module_readdata;

  assign cpu_two_data_master_requests_cpu_two_jtag_debug_module = ({cpu_two_data_master_address_to_slave[19 : 11] , 11'b0} == 20'h80000) & (cpu_two_data_master_read | cpu_two_data_master_write);
  //cpu_two_jtag_debug_module_arb_share_counter set values, which is an e_mux
  assign cpu_two_jtag_debug_module_arb_share_set_values = 1;

  //cpu_two_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
  assign cpu_two_jtag_debug_module_non_bursting_master_requests = cpu_two_data_master_requests_cpu_two_jtag_debug_module |
    cpu_two_instruction_master_requests_cpu_two_jtag_debug_module |
    cpu_two_data_master_requests_cpu_two_jtag_debug_module |
    cpu_two_instruction_master_requests_cpu_two_jtag_debug_module;

  //cpu_two_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
  assign cpu_two_jtag_debug_module_any_bursting_master_saved_grant = 0;

  //cpu_two_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
  assign cpu_two_jtag_debug_module_arb_share_counter_next_value = cpu_two_jtag_debug_module_firsttransfer ? (cpu_two_jtag_debug_module_arb_share_set_values - 1) : |cpu_two_jtag_debug_module_arb_share_counter ? (cpu_two_jtag_debug_module_arb_share_counter - 1) : 0;

  //cpu_two_jtag_debug_module_allgrants all slave grants, which is an e_mux
  assign cpu_two_jtag_debug_module_allgrants = (|cpu_two_jtag_debug_module_grant_vector) |
    (|cpu_two_jtag_debug_module_grant_vector) |
    (|cpu_two_jtag_debug_module_grant_vector) |
    (|cpu_two_jtag_debug_module_grant_vector);

  //cpu_two_jtag_debug_module_end_xfer assignment, which is an e_assign
  assign cpu_two_jtag_debug_module_end_xfer = ~(cpu_two_jtag_debug_module_waits_for_read | cpu_two_jtag_debug_module_waits_for_write);

  //end_xfer_arb_share_counter_term_cpu_two_jtag_debug_module arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_cpu_two_jtag_debug_module = cpu_two_jtag_debug_module_end_xfer & (~cpu_two_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //cpu_two_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
  assign cpu_two_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_two_jtag_debug_module & cpu_two_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_two_jtag_debug_module & ~cpu_two_jtag_debug_module_non_bursting_master_requests);

  //cpu_two_jtag_debug_module_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_jtag_debug_module_arb_share_counter <= 0;
      else if (cpu_two_jtag_debug_module_arb_counter_enable)
          cpu_two_jtag_debug_module_arb_share_counter <= cpu_two_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu_two_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_jtag_debug_module_slavearbiterlockenable <= 0;
      else if ((|cpu_two_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_two_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_two_jtag_debug_module & ~cpu_two_jtag_debug_module_non_bursting_master_requests))
          cpu_two_jtag_debug_module_slavearbiterlockenable <= |cpu_two_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu_two/data_master cpu_two/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_two_data_master_arbiterlock = cpu_two_jtag_debug_module_slavearbiterlockenable & cpu_two_data_master_continuerequest;

  //cpu_two_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign cpu_two_jtag_debug_module_slavearbiterlockenable2 = |cpu_two_jtag_debug_module_arb_share_counter_next_value;

  //cpu_two/data_master cpu_two/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_two_data_master_arbiterlock2 = cpu_two_jtag_debug_module_slavearbiterlockenable2 & cpu_two_data_master_continuerequest;

  //cpu_two/instruction_master cpu_two/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_two_instruction_master_arbiterlock = cpu_two_jtag_debug_module_slavearbiterlockenable & cpu_two_instruction_master_continuerequest;

  //cpu_two/instruction_master cpu_two/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_two_instruction_master_arbiterlock2 = cpu_two_jtag_debug_module_slavearbiterlockenable2 & cpu_two_instruction_master_continuerequest;

  //cpu_two/instruction_master granted cpu_two/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_two_instruction_master_granted_slave_cpu_two_jtag_debug_module <= 0;
      else 
        last_cycle_cpu_two_instruction_master_granted_slave_cpu_two_jtag_debug_module <= cpu_two_instruction_master_saved_grant_cpu_two_jtag_debug_module ? 1 : (cpu_two_jtag_debug_module_arbitration_holdoff_internal | ~cpu_two_instruction_master_requests_cpu_two_jtag_debug_module) ? 0 : last_cycle_cpu_two_instruction_master_granted_slave_cpu_two_jtag_debug_module;
    end


  //cpu_two_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_two_instruction_master_continuerequest = last_cycle_cpu_two_instruction_master_granted_slave_cpu_two_jtag_debug_module & cpu_two_instruction_master_requests_cpu_two_jtag_debug_module;

  //cpu_two_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
  assign cpu_two_jtag_debug_module_any_continuerequest = cpu_two_instruction_master_continuerequest |
    cpu_two_data_master_continuerequest;

  assign cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module = cpu_two_data_master_requests_cpu_two_jtag_debug_module & ~(((~cpu_two_data_master_waitrequest) & cpu_two_data_master_write) | cpu_two_instruction_master_arbiterlock);
  //cpu_two_jtag_debug_module_writedata mux, which is an e_mux
  assign cpu_two_jtag_debug_module_writedata = cpu_two_data_master_writedata;

  assign cpu_two_instruction_master_requests_cpu_two_jtag_debug_module = (({cpu_two_instruction_master_address_to_slave[19 : 11] , 11'b0} == 20'h80000) & (cpu_two_instruction_master_read)) & cpu_two_instruction_master_read;
  //cpu_two/data_master granted cpu_two/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_two_data_master_granted_slave_cpu_two_jtag_debug_module <= 0;
      else 
        last_cycle_cpu_two_data_master_granted_slave_cpu_two_jtag_debug_module <= cpu_two_data_master_saved_grant_cpu_two_jtag_debug_module ? 1 : (cpu_two_jtag_debug_module_arbitration_holdoff_internal | ~cpu_two_data_master_requests_cpu_two_jtag_debug_module) ? 0 : last_cycle_cpu_two_data_master_granted_slave_cpu_two_jtag_debug_module;
    end


  //cpu_two_data_master_continuerequest continued request, which is an e_mux
  assign cpu_two_data_master_continuerequest = last_cycle_cpu_two_data_master_granted_slave_cpu_two_jtag_debug_module & cpu_two_data_master_requests_cpu_two_jtag_debug_module;

  assign cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module = cpu_two_instruction_master_requests_cpu_two_jtag_debug_module & ~((cpu_two_instruction_master_read & ((cpu_two_instruction_master_latency_counter != 0))) | cpu_two_data_master_arbiterlock);
  //local readdatavalid cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module, which is an e_mux
  assign cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module = cpu_two_instruction_master_granted_cpu_two_jtag_debug_module & cpu_two_instruction_master_read & ~cpu_two_jtag_debug_module_waits_for_read;

  //allow new arb cycle for cpu_two/jtag_debug_module, which is an e_assign
  assign cpu_two_jtag_debug_module_allow_new_arb_cycle = ~cpu_two_data_master_arbiterlock & ~cpu_two_instruction_master_arbiterlock;

  //cpu_two/instruction_master assignment into master qualified-requests vector for cpu_two/jtag_debug_module, which is an e_assign
  assign cpu_two_jtag_debug_module_master_qreq_vector[0] = cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module;

  //cpu_two/instruction_master grant cpu_two/jtag_debug_module, which is an e_assign
  assign cpu_two_instruction_master_granted_cpu_two_jtag_debug_module = cpu_two_jtag_debug_module_grant_vector[0];

  //cpu_two/instruction_master saved-grant cpu_two/jtag_debug_module, which is an e_assign
  assign cpu_two_instruction_master_saved_grant_cpu_two_jtag_debug_module = cpu_two_jtag_debug_module_arb_winner[0] && cpu_two_instruction_master_requests_cpu_two_jtag_debug_module;

  //cpu_two/data_master assignment into master qualified-requests vector for cpu_two/jtag_debug_module, which is an e_assign
  assign cpu_two_jtag_debug_module_master_qreq_vector[1] = cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module;

  //cpu_two/data_master grant cpu_two/jtag_debug_module, which is an e_assign
  assign cpu_two_data_master_granted_cpu_two_jtag_debug_module = cpu_two_jtag_debug_module_grant_vector[1];

  //cpu_two/data_master saved-grant cpu_two/jtag_debug_module, which is an e_assign
  assign cpu_two_data_master_saved_grant_cpu_two_jtag_debug_module = cpu_two_jtag_debug_module_arb_winner[1] && cpu_two_data_master_requests_cpu_two_jtag_debug_module;

  //cpu_two/jtag_debug_module chosen-master double-vector, which is an e_assign
  assign cpu_two_jtag_debug_module_chosen_master_double_vector = {cpu_two_jtag_debug_module_master_qreq_vector, cpu_two_jtag_debug_module_master_qreq_vector} & ({~cpu_two_jtag_debug_module_master_qreq_vector, ~cpu_two_jtag_debug_module_master_qreq_vector} + cpu_two_jtag_debug_module_arb_addend);

  //stable onehot encoding of arb winner
  assign cpu_two_jtag_debug_module_arb_winner = (cpu_two_jtag_debug_module_allow_new_arb_cycle & | cpu_two_jtag_debug_module_grant_vector) ? cpu_two_jtag_debug_module_grant_vector : cpu_two_jtag_debug_module_saved_chosen_master_vector;

  //saved cpu_two_jtag_debug_module_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_jtag_debug_module_saved_chosen_master_vector <= 0;
      else if (cpu_two_jtag_debug_module_allow_new_arb_cycle)
          cpu_two_jtag_debug_module_saved_chosen_master_vector <= |cpu_two_jtag_debug_module_grant_vector ? cpu_two_jtag_debug_module_grant_vector : cpu_two_jtag_debug_module_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign cpu_two_jtag_debug_module_grant_vector = {(cpu_two_jtag_debug_module_chosen_master_double_vector[1] | cpu_two_jtag_debug_module_chosen_master_double_vector[3]),
    (cpu_two_jtag_debug_module_chosen_master_double_vector[0] | cpu_two_jtag_debug_module_chosen_master_double_vector[2])};

  //cpu_two/jtag_debug_module chosen master rotated left, which is an e_assign
  assign cpu_two_jtag_debug_module_chosen_master_rot_left = (cpu_two_jtag_debug_module_arb_winner << 1) ? (cpu_two_jtag_debug_module_arb_winner << 1) : 1;

  //cpu_two/jtag_debug_module's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_jtag_debug_module_arb_addend <= 1;
      else if (|cpu_two_jtag_debug_module_grant_vector)
          cpu_two_jtag_debug_module_arb_addend <= cpu_two_jtag_debug_module_end_xfer? cpu_two_jtag_debug_module_chosen_master_rot_left : cpu_two_jtag_debug_module_grant_vector;
    end


  assign cpu_two_jtag_debug_module_begintransfer = cpu_two_jtag_debug_module_begins_xfer;
  //assign lhs ~cpu_two_jtag_debug_module_reset of type reset_n to cpu_two_jtag_debug_module_reset_n, which is an e_assign
  assign cpu_two_jtag_debug_module_reset = ~cpu_two_jtag_debug_module_reset_n;

  //cpu_two_jtag_debug_module_reset_n assignment, which is an e_assign
  assign cpu_two_jtag_debug_module_reset_n = reset_n;

  //assign cpu_two_jtag_debug_module_resetrequest_from_sa = cpu_two_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_two_jtag_debug_module_resetrequest_from_sa = cpu_two_jtag_debug_module_resetrequest;

  assign cpu_two_jtag_debug_module_chipselect = cpu_two_data_master_granted_cpu_two_jtag_debug_module | cpu_two_instruction_master_granted_cpu_two_jtag_debug_module;
  //cpu_two_jtag_debug_module_firsttransfer first transaction, which is an e_assign
  assign cpu_two_jtag_debug_module_firsttransfer = cpu_two_jtag_debug_module_begins_xfer ? cpu_two_jtag_debug_module_unreg_firsttransfer : cpu_two_jtag_debug_module_reg_firsttransfer;

  //cpu_two_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign
  assign cpu_two_jtag_debug_module_unreg_firsttransfer = ~(cpu_two_jtag_debug_module_slavearbiterlockenable & cpu_two_jtag_debug_module_any_continuerequest);

  //cpu_two_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_jtag_debug_module_reg_firsttransfer <= 1'b1;
      else if (cpu_two_jtag_debug_module_begins_xfer)
          cpu_two_jtag_debug_module_reg_firsttransfer <= cpu_two_jtag_debug_module_unreg_firsttransfer;
    end


  //cpu_two_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cpu_two_jtag_debug_module_beginbursttransfer_internal = cpu_two_jtag_debug_module_begins_xfer;

  //cpu_two_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cpu_two_jtag_debug_module_arbitration_holdoff_internal = cpu_two_jtag_debug_module_begins_xfer & cpu_two_jtag_debug_module_firsttransfer;

  //cpu_two_jtag_debug_module_write assignment, which is an e_mux
  assign cpu_two_jtag_debug_module_write = cpu_two_data_master_granted_cpu_two_jtag_debug_module & cpu_two_data_master_write;

  assign shifted_address_to_cpu_two_jtag_debug_module_from_cpu_two_data_master = cpu_two_data_master_address_to_slave;
  //cpu_two_jtag_debug_module_address mux, which is an e_mux
  assign cpu_two_jtag_debug_module_address = (cpu_two_data_master_granted_cpu_two_jtag_debug_module)? (shifted_address_to_cpu_two_jtag_debug_module_from_cpu_two_data_master >> 2) :
    (shifted_address_to_cpu_two_jtag_debug_module_from_cpu_two_instruction_master >> 2);

  assign shifted_address_to_cpu_two_jtag_debug_module_from_cpu_two_instruction_master = cpu_two_instruction_master_address_to_slave;
  //d1_cpu_two_jtag_debug_module_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cpu_two_jtag_debug_module_end_xfer <= 1;
      else 
        d1_cpu_two_jtag_debug_module_end_xfer <= cpu_two_jtag_debug_module_end_xfer;
    end


  //cpu_two_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  assign cpu_two_jtag_debug_module_waits_for_read = cpu_two_jtag_debug_module_in_a_read_cycle & cpu_two_jtag_debug_module_begins_xfer;

  //cpu_two_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  assign cpu_two_jtag_debug_module_in_a_read_cycle = (cpu_two_data_master_granted_cpu_two_jtag_debug_module & cpu_two_data_master_read) | (cpu_two_instruction_master_granted_cpu_two_jtag_debug_module & cpu_two_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cpu_two_jtag_debug_module_in_a_read_cycle;

  //cpu_two_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  assign cpu_two_jtag_debug_module_waits_for_write = cpu_two_jtag_debug_module_in_a_write_cycle & 0;

  //cpu_two_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  assign cpu_two_jtag_debug_module_in_a_write_cycle = cpu_two_data_master_granted_cpu_two_jtag_debug_module & cpu_two_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cpu_two_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu_two_jtag_debug_module_counter = 0;
  //cpu_two_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  assign cpu_two_jtag_debug_module_byteenable = (cpu_two_data_master_granted_cpu_two_jtag_debug_module)? cpu_two_data_master_byteenable :
    -1;

  //debugaccess mux, which is an e_mux
  assign cpu_two_jtag_debug_module_debugaccess = (cpu_two_data_master_granted_cpu_two_jtag_debug_module)? cpu_two_data_master_debugaccess :
    0;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_two/jtag_debug_module enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_two_data_master_granted_cpu_two_jtag_debug_module + cpu_two_instruction_master_granted_cpu_two_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_two_data_master_saved_grant_cpu_two_jtag_debug_module + cpu_two_instruction_master_saved_grant_cpu_two_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_two_data_master_arbitrator (
                                        // inputs:
                                         bridge_one_avalon_slave_irq_from_sa,
                                         bridge_two_avalon_slave_irq_from_sa,
                                         bridge_two_avalon_slave_readdata_from_sa,
                                         bridge_two_avalon_slave_waitrequest_from_sa,
                                         clk,
                                         cpu_two_data_master_address,
                                         cpu_two_data_master_granted_bridge_two_avalon_slave,
                                         cpu_two_data_master_granted_cpu_two_jtag_debug_module,
                                         cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave,
                                         cpu_two_data_master_granted_onchip_mem_two_s1,
                                         cpu_two_data_master_qualified_request_bridge_two_avalon_slave,
                                         cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module,
                                         cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave,
                                         cpu_two_data_master_qualified_request_onchip_mem_two_s1,
                                         cpu_two_data_master_read,
                                         cpu_two_data_master_read_data_valid_bridge_two_avalon_slave,
                                         cpu_two_data_master_read_data_valid_cpu_two_jtag_debug_module,
                                         cpu_two_data_master_read_data_valid_jtag_uart_two_avalon_jtag_slave,
                                         cpu_two_data_master_read_data_valid_onchip_mem_two_s1,
                                         cpu_two_data_master_requests_bridge_two_avalon_slave,
                                         cpu_two_data_master_requests_cpu_two_jtag_debug_module,
                                         cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave,
                                         cpu_two_data_master_requests_onchip_mem_two_s1,
                                         cpu_two_data_master_write,
                                         cpu_two_jtag_debug_module_readdata_from_sa,
                                         d1_bridge_two_avalon_slave_end_xfer,
                                         d1_cpu_two_jtag_debug_module_end_xfer,
                                         d1_jtag_uart_two_avalon_jtag_slave_end_xfer,
                                         d1_onchip_mem_two_s1_end_xfer,
                                         jtag_uart_one_avalon_jtag_slave_irq_from_sa,
                                         jtag_uart_two_avalon_jtag_slave_irq_from_sa,
                                         jtag_uart_two_avalon_jtag_slave_readdata_from_sa,
                                         jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa,
                                         onchip_mem_two_s1_readdata_from_sa,
                                         registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave,
                                         registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1,
                                         reset_n,

                                        // outputs:
                                         cpu_two_data_master_address_to_slave,
                                         cpu_two_data_master_irq,
                                         cpu_two_data_master_readdata,
                                         cpu_two_data_master_waitrequest
                                      )
;

  output  [ 19: 0] cpu_two_data_master_address_to_slave;
  output  [ 31: 0] cpu_two_data_master_irq;
  output  [ 31: 0] cpu_two_data_master_readdata;
  output           cpu_two_data_master_waitrequest;
  input            bridge_one_avalon_slave_irq_from_sa;
  input            bridge_two_avalon_slave_irq_from_sa;
  input   [ 31: 0] bridge_two_avalon_slave_readdata_from_sa;
  input            bridge_two_avalon_slave_waitrequest_from_sa;
  input            clk;
  input   [ 19: 0] cpu_two_data_master_address;
  input            cpu_two_data_master_granted_bridge_two_avalon_slave;
  input            cpu_two_data_master_granted_cpu_two_jtag_debug_module;
  input            cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave;
  input            cpu_two_data_master_granted_onchip_mem_two_s1;
  input            cpu_two_data_master_qualified_request_bridge_two_avalon_slave;
  input            cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module;
  input            cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave;
  input            cpu_two_data_master_qualified_request_onchip_mem_two_s1;
  input            cpu_two_data_master_read;
  input            cpu_two_data_master_read_data_valid_bridge_two_avalon_slave;
  input            cpu_two_data_master_read_data_valid_cpu_two_jtag_debug_module;
  input            cpu_two_data_master_read_data_valid_jtag_uart_two_avalon_jtag_slave;
  input            cpu_two_data_master_read_data_valid_onchip_mem_two_s1;
  input            cpu_two_data_master_requests_bridge_two_avalon_slave;
  input            cpu_two_data_master_requests_cpu_two_jtag_debug_module;
  input            cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave;
  input            cpu_two_data_master_requests_onchip_mem_two_s1;
  input            cpu_two_data_master_write;
  input   [ 31: 0] cpu_two_jtag_debug_module_readdata_from_sa;
  input            d1_bridge_two_avalon_slave_end_xfer;
  input            d1_cpu_two_jtag_debug_module_end_xfer;
  input            d1_jtag_uart_two_avalon_jtag_slave_end_xfer;
  input            d1_onchip_mem_two_s1_end_xfer;
  input            jtag_uart_one_avalon_jtag_slave_irq_from_sa;
  input            jtag_uart_two_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] jtag_uart_two_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa;
  input   [ 31: 0] onchip_mem_two_s1_readdata_from_sa;
  input            registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave;
  input            registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1;
  input            reset_n;

  wire    [ 19: 0] cpu_two_data_master_address_to_slave;
  wire    [ 31: 0] cpu_two_data_master_irq;
  wire    [ 31: 0] cpu_two_data_master_readdata;
  wire             cpu_two_data_master_run;
  reg              cpu_two_data_master_waitrequest;
  wire    [ 31: 0] p1_registered_cpu_two_data_master_readdata;
  wire             r_0;
  reg     [ 31: 0] registered_cpu_two_data_master_readdata;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_two_data_master_qualified_request_bridge_two_avalon_slave | registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave | ~cpu_two_data_master_requests_bridge_two_avalon_slave) & ((~cpu_two_data_master_qualified_request_bridge_two_avalon_slave | ~cpu_two_data_master_read | (registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave & cpu_two_data_master_read))) & ((~cpu_two_data_master_qualified_request_bridge_two_avalon_slave | ~(cpu_two_data_master_read | cpu_two_data_master_write) | (1 & ~bridge_two_avalon_slave_waitrequest_from_sa & (cpu_two_data_master_read | cpu_two_data_master_write)))) & 1 & (cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module | ~cpu_two_data_master_requests_cpu_two_jtag_debug_module) & (cpu_two_data_master_granted_cpu_two_jtag_debug_module | ~cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module) & ((~cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module | ~cpu_two_data_master_read | (1 & 1 & cpu_two_data_master_read))) & ((~cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module | ~cpu_two_data_master_write | (1 & cpu_two_data_master_write))) & 1 & (cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave | ~cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave) & ((~cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave | ~(cpu_two_data_master_read | cpu_two_data_master_write) | (1 & ~jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa & (cpu_two_data_master_read | cpu_two_data_master_write)))) & ((~cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave | ~(cpu_two_data_master_read | cpu_two_data_master_write) | (1 & ~jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa & (cpu_two_data_master_read | cpu_two_data_master_write)))) & 1 & (cpu_two_data_master_qualified_request_onchip_mem_two_s1 | registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1 | ~cpu_two_data_master_requests_onchip_mem_two_s1) & (cpu_two_data_master_granted_onchip_mem_two_s1 | ~cpu_two_data_master_qualified_request_onchip_mem_two_s1) & ((~cpu_two_data_master_qualified_request_onchip_mem_two_s1 | ~cpu_two_data_master_read | (registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1 & cpu_two_data_master_read))) & ((~cpu_two_data_master_qualified_request_onchip_mem_two_s1 | ~(cpu_two_data_master_read | cpu_two_data_master_write) | (1 & (cpu_two_data_master_read | cpu_two_data_master_write))));

  //cascaded wait assignment, which is an e_assign
  assign cpu_two_data_master_run = r_0;

  //irq assign, which is an e_assign
  assign cpu_two_data_master_irq = {1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    bridge_two_avalon_slave_irq_from_sa,
    jtag_uart_two_avalon_jtag_slave_irq_from_sa,
    bridge_one_avalon_slave_irq_from_sa,
    jtag_uart_one_avalon_jtag_slave_irq_from_sa};

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_two_data_master_address_to_slave = cpu_two_data_master_address[19 : 0];

  //cpu_two/data_master readdata mux, which is an e_mux
  assign cpu_two_data_master_readdata = ({32 {~cpu_two_data_master_requests_bridge_two_avalon_slave}} | bridge_two_avalon_slave_readdata_from_sa) &
    ({32 {~cpu_two_data_master_requests_cpu_two_jtag_debug_module}} | cpu_two_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave}} | registered_cpu_two_data_master_readdata) &
    ({32 {~cpu_two_data_master_requests_onchip_mem_two_s1}} | onchip_mem_two_s1_readdata_from_sa);

  //actual waitrequest port, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_data_master_waitrequest <= ~0;
      else 
        cpu_two_data_master_waitrequest <= ~((~(cpu_two_data_master_read | cpu_two_data_master_write))? 0: (cpu_two_data_master_run & cpu_two_data_master_waitrequest));
    end


  //unpredictable registered wait state incoming data, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          registered_cpu_two_data_master_readdata <= 0;
      else 
        registered_cpu_two_data_master_readdata <= p1_registered_cpu_two_data_master_readdata;
    end


  //registered readdata mux, which is an e_mux
  assign p1_registered_cpu_two_data_master_readdata = {32 {~cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave}} | jtag_uart_two_avalon_jtag_slave_readdata_from_sa;


endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_two_instruction_master_arbitrator (
                                               // inputs:
                                                clk,
                                                cpu_two_instruction_master_address,
                                                cpu_two_instruction_master_granted_cpu_two_jtag_debug_module,
                                                cpu_two_instruction_master_granted_onchip_mem_two_s1,
                                                cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module,
                                                cpu_two_instruction_master_qualified_request_onchip_mem_two_s1,
                                                cpu_two_instruction_master_read,
                                                cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module,
                                                cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1,
                                                cpu_two_instruction_master_requests_cpu_two_jtag_debug_module,
                                                cpu_two_instruction_master_requests_onchip_mem_two_s1,
                                                cpu_two_jtag_debug_module_readdata_from_sa,
                                                d1_cpu_two_jtag_debug_module_end_xfer,
                                                d1_onchip_mem_two_s1_end_xfer,
                                                onchip_mem_two_s1_readdata_from_sa,
                                                reset_n,

                                               // outputs:
                                                cpu_two_instruction_master_address_to_slave,
                                                cpu_two_instruction_master_latency_counter,
                                                cpu_two_instruction_master_readdata,
                                                cpu_two_instruction_master_readdatavalid,
                                                cpu_two_instruction_master_waitrequest
                                             )
;

  output  [ 19: 0] cpu_two_instruction_master_address_to_slave;
  output           cpu_two_instruction_master_latency_counter;
  output  [ 31: 0] cpu_two_instruction_master_readdata;
  output           cpu_two_instruction_master_readdatavalid;
  output           cpu_two_instruction_master_waitrequest;
  input            clk;
  input   [ 19: 0] cpu_two_instruction_master_address;
  input            cpu_two_instruction_master_granted_cpu_two_jtag_debug_module;
  input            cpu_two_instruction_master_granted_onchip_mem_two_s1;
  input            cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module;
  input            cpu_two_instruction_master_qualified_request_onchip_mem_two_s1;
  input            cpu_two_instruction_master_read;
  input            cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module;
  input            cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1;
  input            cpu_two_instruction_master_requests_cpu_two_jtag_debug_module;
  input            cpu_two_instruction_master_requests_onchip_mem_two_s1;
  input   [ 31: 0] cpu_two_jtag_debug_module_readdata_from_sa;
  input            d1_cpu_two_jtag_debug_module_end_xfer;
  input            d1_onchip_mem_two_s1_end_xfer;
  input   [ 31: 0] onchip_mem_two_s1_readdata_from_sa;
  input            reset_n;

  reg              active_and_waiting_last_time;
  reg     [ 19: 0] cpu_two_instruction_master_address_last_time;
  wire    [ 19: 0] cpu_two_instruction_master_address_to_slave;
  wire             cpu_two_instruction_master_is_granted_some_slave;
  reg              cpu_two_instruction_master_latency_counter;
  reg              cpu_two_instruction_master_read_but_no_slave_selected;
  reg              cpu_two_instruction_master_read_last_time;
  wire    [ 31: 0] cpu_two_instruction_master_readdata;
  wire             cpu_two_instruction_master_readdatavalid;
  wire             cpu_two_instruction_master_run;
  wire             cpu_two_instruction_master_waitrequest;
  wire             latency_load_value;
  wire             p1_cpu_two_instruction_master_latency_counter;
  wire             pre_flush_cpu_two_instruction_master_readdatavalid;
  wire             r_0;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module | ~cpu_two_instruction_master_requests_cpu_two_jtag_debug_module) & (cpu_two_instruction_master_granted_cpu_two_jtag_debug_module | ~cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module) & ((~cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module | ~cpu_two_instruction_master_read | (1 & ~d1_cpu_two_jtag_debug_module_end_xfer & cpu_two_instruction_master_read))) & 1 & (cpu_two_instruction_master_qualified_request_onchip_mem_two_s1 | ~cpu_two_instruction_master_requests_onchip_mem_two_s1) & (cpu_two_instruction_master_granted_onchip_mem_two_s1 | ~cpu_two_instruction_master_qualified_request_onchip_mem_two_s1) & ((~cpu_two_instruction_master_qualified_request_onchip_mem_two_s1 | ~cpu_two_instruction_master_read | (1 & cpu_two_instruction_master_read)));

  //cascaded wait assignment, which is an e_assign
  assign cpu_two_instruction_master_run = r_0;

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_two_instruction_master_address_to_slave = {5'b10000,
    cpu_two_instruction_master_address[14],
    2'b0,
    cpu_two_instruction_master_address[11 : 0]};

  //cpu_two_instruction_master_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_instruction_master_read_but_no_slave_selected <= 0;
      else 
        cpu_two_instruction_master_read_but_no_slave_selected <= cpu_two_instruction_master_read & cpu_two_instruction_master_run & ~cpu_two_instruction_master_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign cpu_two_instruction_master_is_granted_some_slave = cpu_two_instruction_master_granted_cpu_two_jtag_debug_module |
    cpu_two_instruction_master_granted_onchip_mem_two_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_cpu_two_instruction_master_readdatavalid = cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign cpu_two_instruction_master_readdatavalid = cpu_two_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_two_instruction_master_readdatavalid |
    cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module |
    cpu_two_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_two_instruction_master_readdatavalid;

  //cpu_two/instruction_master readdata mux, which is an e_mux
  assign cpu_two_instruction_master_readdata = ({32 {~(cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module & cpu_two_instruction_master_read)}} | cpu_two_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1}} | onchip_mem_two_s1_readdata_from_sa);

  //actual waitrequest port, which is an e_assign
  assign cpu_two_instruction_master_waitrequest = ~cpu_two_instruction_master_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_instruction_master_latency_counter <= 0;
      else 
        cpu_two_instruction_master_latency_counter <= p1_cpu_two_instruction_master_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_cpu_two_instruction_master_latency_counter = ((cpu_two_instruction_master_run & cpu_two_instruction_master_read))? latency_load_value :
    (cpu_two_instruction_master_latency_counter)? cpu_two_instruction_master_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = {1 {cpu_two_instruction_master_requests_onchip_mem_two_s1}} & 1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_two_instruction_master_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_instruction_master_address_last_time <= 0;
      else 
        cpu_two_instruction_master_address_last_time <= cpu_two_instruction_master_address;
    end


  //cpu_two/instruction_master waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else 
        active_and_waiting_last_time <= cpu_two_instruction_master_waitrequest & (cpu_two_instruction_master_read);
    end


  //cpu_two_instruction_master_address matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_two_instruction_master_address != cpu_two_instruction_master_address_last_time))
        begin
          $write("%0d ns: cpu_two_instruction_master_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_two_instruction_master_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_instruction_master_read_last_time <= 0;
      else 
        cpu_two_instruction_master_read_last_time <= cpu_two_instruction_master_read;
    end


  //cpu_two_instruction_master_read matches last port_name, which is an e_process
  always @(posedge clk)
    begin
      if (active_and_waiting_last_time & (cpu_two_instruction_master_read != cpu_two_instruction_master_read_last_time))
        begin
          $write("%0d ns: cpu_two_instruction_master_read did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module jtag_uart_one_avalon_jtag_slave_arbitrator (
                                                    // inputs:
                                                     clk,
                                                     cpu_one_data_master_address_to_slave,
                                                     cpu_one_data_master_read,
                                                     cpu_one_data_master_waitrequest,
                                                     cpu_one_data_master_write,
                                                     cpu_one_data_master_writedata,
                                                     jtag_uart_one_avalon_jtag_slave_dataavailable,
                                                     jtag_uart_one_avalon_jtag_slave_irq,
                                                     jtag_uart_one_avalon_jtag_slave_readdata,
                                                     jtag_uart_one_avalon_jtag_slave_readyfordata,
                                                     jtag_uart_one_avalon_jtag_slave_waitrequest,
                                                     reset_n,

                                                    // outputs:
                                                     cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave,
                                                     cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave,
                                                     cpu_one_data_master_read_data_valid_jtag_uart_one_avalon_jtag_slave,
                                                     cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave,
                                                     d1_jtag_uart_one_avalon_jtag_slave_end_xfer,
                                                     jtag_uart_one_avalon_jtag_slave_address,
                                                     jtag_uart_one_avalon_jtag_slave_chipselect,
                                                     jtag_uart_one_avalon_jtag_slave_dataavailable_from_sa,
                                                     jtag_uart_one_avalon_jtag_slave_irq_from_sa,
                                                     jtag_uart_one_avalon_jtag_slave_read_n,
                                                     jtag_uart_one_avalon_jtag_slave_readdata_from_sa,
                                                     jtag_uart_one_avalon_jtag_slave_readyfordata_from_sa,
                                                     jtag_uart_one_avalon_jtag_slave_reset_n,
                                                     jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa,
                                                     jtag_uart_one_avalon_jtag_slave_write_n,
                                                     jtag_uart_one_avalon_jtag_slave_writedata
                                                  )
;

  output           cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave;
  output           cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave;
  output           cpu_one_data_master_read_data_valid_jtag_uart_one_avalon_jtag_slave;
  output           cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave;
  output           d1_jtag_uart_one_avalon_jtag_slave_end_xfer;
  output           jtag_uart_one_avalon_jtag_slave_address;
  output           jtag_uart_one_avalon_jtag_slave_chipselect;
  output           jtag_uart_one_avalon_jtag_slave_dataavailable_from_sa;
  output           jtag_uart_one_avalon_jtag_slave_irq_from_sa;
  output           jtag_uart_one_avalon_jtag_slave_read_n;
  output  [ 31: 0] jtag_uart_one_avalon_jtag_slave_readdata_from_sa;
  output           jtag_uart_one_avalon_jtag_slave_readyfordata_from_sa;
  output           jtag_uart_one_avalon_jtag_slave_reset_n;
  output           jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa;
  output           jtag_uart_one_avalon_jtag_slave_write_n;
  output  [ 31: 0] jtag_uart_one_avalon_jtag_slave_writedata;
  input            clk;
  input   [ 19: 0] cpu_one_data_master_address_to_slave;
  input            cpu_one_data_master_read;
  input            cpu_one_data_master_waitrequest;
  input            cpu_one_data_master_write;
  input   [ 31: 0] cpu_one_data_master_writedata;
  input            jtag_uart_one_avalon_jtag_slave_dataavailable;
  input            jtag_uart_one_avalon_jtag_slave_irq;
  input   [ 31: 0] jtag_uart_one_avalon_jtag_slave_readdata;
  input            jtag_uart_one_avalon_jtag_slave_readyfordata;
  input            jtag_uart_one_avalon_jtag_slave_waitrequest;
  input            reset_n;

  wire             cpu_one_data_master_arbiterlock;
  wire             cpu_one_data_master_arbiterlock2;
  wire             cpu_one_data_master_continuerequest;
  wire             cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave;
  wire             cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave;
  wire             cpu_one_data_master_read_data_valid_jtag_uart_one_avalon_jtag_slave;
  wire             cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave;
  wire             cpu_one_data_master_saved_grant_jtag_uart_one_avalon_jtag_slave;
  reg              d1_jtag_uart_one_avalon_jtag_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_jtag_uart_one_avalon_jtag_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             jtag_uart_one_avalon_jtag_slave_address;
  wire             jtag_uart_one_avalon_jtag_slave_allgrants;
  wire             jtag_uart_one_avalon_jtag_slave_allow_new_arb_cycle;
  wire             jtag_uart_one_avalon_jtag_slave_any_bursting_master_saved_grant;
  wire             jtag_uart_one_avalon_jtag_slave_any_continuerequest;
  wire             jtag_uart_one_avalon_jtag_slave_arb_counter_enable;
  reg              jtag_uart_one_avalon_jtag_slave_arb_share_counter;
  wire             jtag_uart_one_avalon_jtag_slave_arb_share_counter_next_value;
  wire             jtag_uart_one_avalon_jtag_slave_arb_share_set_values;
  wire             jtag_uart_one_avalon_jtag_slave_beginbursttransfer_internal;
  wire             jtag_uart_one_avalon_jtag_slave_begins_xfer;
  wire             jtag_uart_one_avalon_jtag_slave_chipselect;
  wire             jtag_uart_one_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_one_avalon_jtag_slave_end_xfer;
  wire             jtag_uart_one_avalon_jtag_slave_firsttransfer;
  wire             jtag_uart_one_avalon_jtag_slave_grant_vector;
  wire             jtag_uart_one_avalon_jtag_slave_in_a_read_cycle;
  wire             jtag_uart_one_avalon_jtag_slave_in_a_write_cycle;
  wire             jtag_uart_one_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_one_avalon_jtag_slave_master_qreq_vector;
  wire             jtag_uart_one_avalon_jtag_slave_non_bursting_master_requests;
  wire             jtag_uart_one_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_one_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_one_avalon_jtag_slave_readyfordata_from_sa;
  reg              jtag_uart_one_avalon_jtag_slave_reg_firsttransfer;
  wire             jtag_uart_one_avalon_jtag_slave_reset_n;
  reg              jtag_uart_one_avalon_jtag_slave_slavearbiterlockenable;
  wire             jtag_uart_one_avalon_jtag_slave_slavearbiterlockenable2;
  wire             jtag_uart_one_avalon_jtag_slave_unreg_firsttransfer;
  wire             jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_one_avalon_jtag_slave_waits_for_read;
  wire             jtag_uart_one_avalon_jtag_slave_waits_for_write;
  wire             jtag_uart_one_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_one_avalon_jtag_slave_writedata;
  wire    [ 19: 0] shifted_address_to_jtag_uart_one_avalon_jtag_slave_from_cpu_one_data_master;
  wire             wait_for_jtag_uart_one_avalon_jtag_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~jtag_uart_one_avalon_jtag_slave_end_xfer;
    end


  assign jtag_uart_one_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave));
  //assign jtag_uart_one_avalon_jtag_slave_readdata_from_sa = jtag_uart_one_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_readdata_from_sa = jtag_uart_one_avalon_jtag_slave_readdata;

  assign cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave = ({cpu_one_data_master_address_to_slave[19 : 3] , 3'b0} == 20'h88000) & (cpu_one_data_master_read | cpu_one_data_master_write);
  //assign jtag_uart_one_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_one_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_one_avalon_jtag_slave_dataavailable;

  //assign jtag_uart_one_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_one_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_one_avalon_jtag_slave_readyfordata;

  //assign jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_one_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_one_avalon_jtag_slave_waitrequest;

  //jtag_uart_one_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
  assign jtag_uart_one_avalon_jtag_slave_arb_share_set_values = 1;

  //jtag_uart_one_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
  assign jtag_uart_one_avalon_jtag_slave_non_bursting_master_requests = cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave;

  //jtag_uart_one_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign jtag_uart_one_avalon_jtag_slave_any_bursting_master_saved_grant = 0;

  //jtag_uart_one_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_one_avalon_jtag_slave_firsttransfer ? (jtag_uart_one_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_one_avalon_jtag_slave_arb_share_counter ? (jtag_uart_one_avalon_jtag_slave_arb_share_counter - 1) : 0;

  //jtag_uart_one_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
  assign jtag_uart_one_avalon_jtag_slave_allgrants = |jtag_uart_one_avalon_jtag_slave_grant_vector;

  //jtag_uart_one_avalon_jtag_slave_end_xfer assignment, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_end_xfer = ~(jtag_uart_one_avalon_jtag_slave_waits_for_read | jtag_uart_one_avalon_jtag_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_jtag_uart_one_avalon_jtag_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_jtag_uart_one_avalon_jtag_slave = jtag_uart_one_avalon_jtag_slave_end_xfer & (~jtag_uart_one_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //jtag_uart_one_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_one_avalon_jtag_slave & jtag_uart_one_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_one_avalon_jtag_slave & ~jtag_uart_one_avalon_jtag_slave_non_bursting_master_requests);

  //jtag_uart_one_avalon_jtag_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_one_avalon_jtag_slave_arb_share_counter <= 0;
      else if (jtag_uart_one_avalon_jtag_slave_arb_counter_enable)
          jtag_uart_one_avalon_jtag_slave_arb_share_counter <= jtag_uart_one_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //jtag_uart_one_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_one_avalon_jtag_slave_slavearbiterlockenable <= 0;
      else if ((|jtag_uart_one_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_one_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_one_avalon_jtag_slave & ~jtag_uart_one_avalon_jtag_slave_non_bursting_master_requests))
          jtag_uart_one_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_one_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //cpu_one/data_master jtag_uart_one/avalon_jtag_slave arbiterlock, which is an e_assign
  assign cpu_one_data_master_arbiterlock = jtag_uart_one_avalon_jtag_slave_slavearbiterlockenable & cpu_one_data_master_continuerequest;

  //jtag_uart_one_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_one_avalon_jtag_slave_arb_share_counter_next_value;

  //cpu_one/data_master jtag_uart_one/avalon_jtag_slave arbiterlock2, which is an e_assign
  assign cpu_one_data_master_arbiterlock2 = jtag_uart_one_avalon_jtag_slave_slavearbiterlockenable2 & cpu_one_data_master_continuerequest;

  //jtag_uart_one_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_any_continuerequest = 1;

  //cpu_one_data_master_continuerequest continued request, which is an e_assign
  assign cpu_one_data_master_continuerequest = 1;

  assign cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave = cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave & ~((cpu_one_data_master_read & (~cpu_one_data_master_waitrequest)) | ((~cpu_one_data_master_waitrequest) & cpu_one_data_master_write));
  //jtag_uart_one_avalon_jtag_slave_writedata mux, which is an e_mux
  assign jtag_uart_one_avalon_jtag_slave_writedata = cpu_one_data_master_writedata;

  //master is always granted when requested
  assign cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave = cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave;

  //cpu_one/data_master saved-grant jtag_uart_one/avalon_jtag_slave, which is an e_assign
  assign cpu_one_data_master_saved_grant_jtag_uart_one_avalon_jtag_slave = cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave;

  //allow new arb cycle for jtag_uart_one/avalon_jtag_slave, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign jtag_uart_one_avalon_jtag_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign jtag_uart_one_avalon_jtag_slave_master_qreq_vector = 1;

  //jtag_uart_one_avalon_jtag_slave_reset_n assignment, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_reset_n = reset_n;

  assign jtag_uart_one_avalon_jtag_slave_chipselect = cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave;
  //jtag_uart_one_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_firsttransfer = jtag_uart_one_avalon_jtag_slave_begins_xfer ? jtag_uart_one_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_one_avalon_jtag_slave_reg_firsttransfer;

  //jtag_uart_one_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_one_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_one_avalon_jtag_slave_any_continuerequest);

  //jtag_uart_one_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_one_avalon_jtag_slave_reg_firsttransfer <= 1'b1;
      else if (jtag_uart_one_avalon_jtag_slave_begins_xfer)
          jtag_uart_one_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_one_avalon_jtag_slave_unreg_firsttransfer;
    end


  //jtag_uart_one_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_one_avalon_jtag_slave_begins_xfer;

  //~jtag_uart_one_avalon_jtag_slave_read_n assignment, which is an e_mux
  assign jtag_uart_one_avalon_jtag_slave_read_n = ~(cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave & cpu_one_data_master_read);

  //~jtag_uart_one_avalon_jtag_slave_write_n assignment, which is an e_mux
  assign jtag_uart_one_avalon_jtag_slave_write_n = ~(cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave & cpu_one_data_master_write);

  assign shifted_address_to_jtag_uart_one_avalon_jtag_slave_from_cpu_one_data_master = cpu_one_data_master_address_to_slave;
  //jtag_uart_one_avalon_jtag_slave_address mux, which is an e_mux
  assign jtag_uart_one_avalon_jtag_slave_address = shifted_address_to_jtag_uart_one_avalon_jtag_slave_from_cpu_one_data_master >> 2;

  //d1_jtag_uart_one_avalon_jtag_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_jtag_uart_one_avalon_jtag_slave_end_xfer <= 1;
      else 
        d1_jtag_uart_one_avalon_jtag_slave_end_xfer <= jtag_uart_one_avalon_jtag_slave_end_xfer;
    end


  //jtag_uart_one_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
  assign jtag_uart_one_avalon_jtag_slave_waits_for_read = jtag_uart_one_avalon_jtag_slave_in_a_read_cycle & jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_one_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_in_a_read_cycle = cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave & cpu_one_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = jtag_uart_one_avalon_jtag_slave_in_a_read_cycle;

  //jtag_uart_one_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
  assign jtag_uart_one_avalon_jtag_slave_waits_for_write = jtag_uart_one_avalon_jtag_slave_in_a_write_cycle & jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_one_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_in_a_write_cycle = cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave & cpu_one_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = jtag_uart_one_avalon_jtag_slave_in_a_write_cycle;

  assign wait_for_jtag_uart_one_avalon_jtag_slave_counter = 0;
  //assign jtag_uart_one_avalon_jtag_slave_irq_from_sa = jtag_uart_one_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_one_avalon_jtag_slave_irq_from_sa = jtag_uart_one_avalon_jtag_slave_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //jtag_uart_one/avalon_jtag_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module jtag_uart_two_avalon_jtag_slave_arbitrator (
                                                    // inputs:
                                                     clk,
                                                     cpu_two_data_master_address_to_slave,
                                                     cpu_two_data_master_read,
                                                     cpu_two_data_master_waitrequest,
                                                     cpu_two_data_master_write,
                                                     cpu_two_data_master_writedata,
                                                     jtag_uart_two_avalon_jtag_slave_dataavailable,
                                                     jtag_uart_two_avalon_jtag_slave_irq,
                                                     jtag_uart_two_avalon_jtag_slave_readdata,
                                                     jtag_uart_two_avalon_jtag_slave_readyfordata,
                                                     jtag_uart_two_avalon_jtag_slave_waitrequest,
                                                     reset_n,

                                                    // outputs:
                                                     cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave,
                                                     cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave,
                                                     cpu_two_data_master_read_data_valid_jtag_uart_two_avalon_jtag_slave,
                                                     cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave,
                                                     d1_jtag_uart_two_avalon_jtag_slave_end_xfer,
                                                     jtag_uart_two_avalon_jtag_slave_address,
                                                     jtag_uart_two_avalon_jtag_slave_chipselect,
                                                     jtag_uart_two_avalon_jtag_slave_dataavailable_from_sa,
                                                     jtag_uart_two_avalon_jtag_slave_irq_from_sa,
                                                     jtag_uart_two_avalon_jtag_slave_read_n,
                                                     jtag_uart_two_avalon_jtag_slave_readdata_from_sa,
                                                     jtag_uart_two_avalon_jtag_slave_readyfordata_from_sa,
                                                     jtag_uart_two_avalon_jtag_slave_reset_n,
                                                     jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa,
                                                     jtag_uart_two_avalon_jtag_slave_write_n,
                                                     jtag_uart_two_avalon_jtag_slave_writedata
                                                  )
;

  output           cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave;
  output           cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave;
  output           cpu_two_data_master_read_data_valid_jtag_uart_two_avalon_jtag_slave;
  output           cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave;
  output           d1_jtag_uart_two_avalon_jtag_slave_end_xfer;
  output           jtag_uart_two_avalon_jtag_slave_address;
  output           jtag_uart_two_avalon_jtag_slave_chipselect;
  output           jtag_uart_two_avalon_jtag_slave_dataavailable_from_sa;
  output           jtag_uart_two_avalon_jtag_slave_irq_from_sa;
  output           jtag_uart_two_avalon_jtag_slave_read_n;
  output  [ 31: 0] jtag_uart_two_avalon_jtag_slave_readdata_from_sa;
  output           jtag_uart_two_avalon_jtag_slave_readyfordata_from_sa;
  output           jtag_uart_two_avalon_jtag_slave_reset_n;
  output           jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa;
  output           jtag_uart_two_avalon_jtag_slave_write_n;
  output  [ 31: 0] jtag_uart_two_avalon_jtag_slave_writedata;
  input            clk;
  input   [ 19: 0] cpu_two_data_master_address_to_slave;
  input            cpu_two_data_master_read;
  input            cpu_two_data_master_waitrequest;
  input            cpu_two_data_master_write;
  input   [ 31: 0] cpu_two_data_master_writedata;
  input            jtag_uart_two_avalon_jtag_slave_dataavailable;
  input            jtag_uart_two_avalon_jtag_slave_irq;
  input   [ 31: 0] jtag_uart_two_avalon_jtag_slave_readdata;
  input            jtag_uart_two_avalon_jtag_slave_readyfordata;
  input            jtag_uart_two_avalon_jtag_slave_waitrequest;
  input            reset_n;

  wire             cpu_two_data_master_arbiterlock;
  wire             cpu_two_data_master_arbiterlock2;
  wire             cpu_two_data_master_continuerequest;
  wire             cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave;
  wire             cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave;
  wire             cpu_two_data_master_read_data_valid_jtag_uart_two_avalon_jtag_slave;
  wire             cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave;
  wire             cpu_two_data_master_saved_grant_jtag_uart_two_avalon_jtag_slave;
  reg              d1_jtag_uart_two_avalon_jtag_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_jtag_uart_two_avalon_jtag_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             jtag_uart_two_avalon_jtag_slave_address;
  wire             jtag_uart_two_avalon_jtag_slave_allgrants;
  wire             jtag_uart_two_avalon_jtag_slave_allow_new_arb_cycle;
  wire             jtag_uart_two_avalon_jtag_slave_any_bursting_master_saved_grant;
  wire             jtag_uart_two_avalon_jtag_slave_any_continuerequest;
  wire             jtag_uart_two_avalon_jtag_slave_arb_counter_enable;
  reg              jtag_uart_two_avalon_jtag_slave_arb_share_counter;
  wire             jtag_uart_two_avalon_jtag_slave_arb_share_counter_next_value;
  wire             jtag_uart_two_avalon_jtag_slave_arb_share_set_values;
  wire             jtag_uart_two_avalon_jtag_slave_beginbursttransfer_internal;
  wire             jtag_uart_two_avalon_jtag_slave_begins_xfer;
  wire             jtag_uart_two_avalon_jtag_slave_chipselect;
  wire             jtag_uart_two_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_two_avalon_jtag_slave_end_xfer;
  wire             jtag_uart_two_avalon_jtag_slave_firsttransfer;
  wire             jtag_uart_two_avalon_jtag_slave_grant_vector;
  wire             jtag_uart_two_avalon_jtag_slave_in_a_read_cycle;
  wire             jtag_uart_two_avalon_jtag_slave_in_a_write_cycle;
  wire             jtag_uart_two_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_two_avalon_jtag_slave_master_qreq_vector;
  wire             jtag_uart_two_avalon_jtag_slave_non_bursting_master_requests;
  wire             jtag_uart_two_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_two_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_two_avalon_jtag_slave_readyfordata_from_sa;
  reg              jtag_uart_two_avalon_jtag_slave_reg_firsttransfer;
  wire             jtag_uart_two_avalon_jtag_slave_reset_n;
  reg              jtag_uart_two_avalon_jtag_slave_slavearbiterlockenable;
  wire             jtag_uart_two_avalon_jtag_slave_slavearbiterlockenable2;
  wire             jtag_uart_two_avalon_jtag_slave_unreg_firsttransfer;
  wire             jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_two_avalon_jtag_slave_waits_for_read;
  wire             jtag_uart_two_avalon_jtag_slave_waits_for_write;
  wire             jtag_uart_two_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_two_avalon_jtag_slave_writedata;
  wire    [ 19: 0] shifted_address_to_jtag_uart_two_avalon_jtag_slave_from_cpu_two_data_master;
  wire             wait_for_jtag_uart_two_avalon_jtag_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~jtag_uart_two_avalon_jtag_slave_end_xfer;
    end


  assign jtag_uart_two_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave));
  //assign jtag_uart_two_avalon_jtag_slave_readdata_from_sa = jtag_uart_two_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_readdata_from_sa = jtag_uart_two_avalon_jtag_slave_readdata;

  assign cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave = ({cpu_two_data_master_address_to_slave[19 : 3] , 3'b0} == 20'h88000) & (cpu_two_data_master_read | cpu_two_data_master_write);
  //assign jtag_uart_two_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_two_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_two_avalon_jtag_slave_dataavailable;

  //assign jtag_uart_two_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_two_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_two_avalon_jtag_slave_readyfordata;

  //assign jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_two_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_two_avalon_jtag_slave_waitrequest;

  //jtag_uart_two_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
  assign jtag_uart_two_avalon_jtag_slave_arb_share_set_values = 1;

  //jtag_uart_two_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
  assign jtag_uart_two_avalon_jtag_slave_non_bursting_master_requests = cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave;

  //jtag_uart_two_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign jtag_uart_two_avalon_jtag_slave_any_bursting_master_saved_grant = 0;

  //jtag_uart_two_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_two_avalon_jtag_slave_firsttransfer ? (jtag_uart_two_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_two_avalon_jtag_slave_arb_share_counter ? (jtag_uart_two_avalon_jtag_slave_arb_share_counter - 1) : 0;

  //jtag_uart_two_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
  assign jtag_uart_two_avalon_jtag_slave_allgrants = |jtag_uart_two_avalon_jtag_slave_grant_vector;

  //jtag_uart_two_avalon_jtag_slave_end_xfer assignment, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_end_xfer = ~(jtag_uart_two_avalon_jtag_slave_waits_for_read | jtag_uart_two_avalon_jtag_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_jtag_uart_two_avalon_jtag_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_jtag_uart_two_avalon_jtag_slave = jtag_uart_two_avalon_jtag_slave_end_xfer & (~jtag_uart_two_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //jtag_uart_two_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_two_avalon_jtag_slave & jtag_uart_two_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_two_avalon_jtag_slave & ~jtag_uart_two_avalon_jtag_slave_non_bursting_master_requests);

  //jtag_uart_two_avalon_jtag_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_two_avalon_jtag_slave_arb_share_counter <= 0;
      else if (jtag_uart_two_avalon_jtag_slave_arb_counter_enable)
          jtag_uart_two_avalon_jtag_slave_arb_share_counter <= jtag_uart_two_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //jtag_uart_two_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_two_avalon_jtag_slave_slavearbiterlockenable <= 0;
      else if ((|jtag_uart_two_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_two_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_two_avalon_jtag_slave & ~jtag_uart_two_avalon_jtag_slave_non_bursting_master_requests))
          jtag_uart_two_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_two_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //cpu_two/data_master jtag_uart_two/avalon_jtag_slave arbiterlock, which is an e_assign
  assign cpu_two_data_master_arbiterlock = jtag_uart_two_avalon_jtag_slave_slavearbiterlockenable & cpu_two_data_master_continuerequest;

  //jtag_uart_two_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_two_avalon_jtag_slave_arb_share_counter_next_value;

  //cpu_two/data_master jtag_uart_two/avalon_jtag_slave arbiterlock2, which is an e_assign
  assign cpu_two_data_master_arbiterlock2 = jtag_uart_two_avalon_jtag_slave_slavearbiterlockenable2 & cpu_two_data_master_continuerequest;

  //jtag_uart_two_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_any_continuerequest = 1;

  //cpu_two_data_master_continuerequest continued request, which is an e_assign
  assign cpu_two_data_master_continuerequest = 1;

  assign cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave = cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave & ~((cpu_two_data_master_read & (~cpu_two_data_master_waitrequest)) | ((~cpu_two_data_master_waitrequest) & cpu_two_data_master_write));
  //jtag_uart_two_avalon_jtag_slave_writedata mux, which is an e_mux
  assign jtag_uart_two_avalon_jtag_slave_writedata = cpu_two_data_master_writedata;

  //master is always granted when requested
  assign cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave = cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave;

  //cpu_two/data_master saved-grant jtag_uart_two/avalon_jtag_slave, which is an e_assign
  assign cpu_two_data_master_saved_grant_jtag_uart_two_avalon_jtag_slave = cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave;

  //allow new arb cycle for jtag_uart_two/avalon_jtag_slave, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign jtag_uart_two_avalon_jtag_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign jtag_uart_two_avalon_jtag_slave_master_qreq_vector = 1;

  //jtag_uart_two_avalon_jtag_slave_reset_n assignment, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_reset_n = reset_n;

  assign jtag_uart_two_avalon_jtag_slave_chipselect = cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave;
  //jtag_uart_two_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_firsttransfer = jtag_uart_two_avalon_jtag_slave_begins_xfer ? jtag_uart_two_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_two_avalon_jtag_slave_reg_firsttransfer;

  //jtag_uart_two_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_two_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_two_avalon_jtag_slave_any_continuerequest);

  //jtag_uart_two_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_two_avalon_jtag_slave_reg_firsttransfer <= 1'b1;
      else if (jtag_uart_two_avalon_jtag_slave_begins_xfer)
          jtag_uart_two_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_two_avalon_jtag_slave_unreg_firsttransfer;
    end


  //jtag_uart_two_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_two_avalon_jtag_slave_begins_xfer;

  //~jtag_uart_two_avalon_jtag_slave_read_n assignment, which is an e_mux
  assign jtag_uart_two_avalon_jtag_slave_read_n = ~(cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave & cpu_two_data_master_read);

  //~jtag_uart_two_avalon_jtag_slave_write_n assignment, which is an e_mux
  assign jtag_uart_two_avalon_jtag_slave_write_n = ~(cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave & cpu_two_data_master_write);

  assign shifted_address_to_jtag_uart_two_avalon_jtag_slave_from_cpu_two_data_master = cpu_two_data_master_address_to_slave;
  //jtag_uart_two_avalon_jtag_slave_address mux, which is an e_mux
  assign jtag_uart_two_avalon_jtag_slave_address = shifted_address_to_jtag_uart_two_avalon_jtag_slave_from_cpu_two_data_master >> 2;

  //d1_jtag_uart_two_avalon_jtag_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_jtag_uart_two_avalon_jtag_slave_end_xfer <= 1;
      else 
        d1_jtag_uart_two_avalon_jtag_slave_end_xfer <= jtag_uart_two_avalon_jtag_slave_end_xfer;
    end


  //jtag_uart_two_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
  assign jtag_uart_two_avalon_jtag_slave_waits_for_read = jtag_uart_two_avalon_jtag_slave_in_a_read_cycle & jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_two_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_in_a_read_cycle = cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave & cpu_two_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = jtag_uart_two_avalon_jtag_slave_in_a_read_cycle;

  //jtag_uart_two_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
  assign jtag_uart_two_avalon_jtag_slave_waits_for_write = jtag_uart_two_avalon_jtag_slave_in_a_write_cycle & jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_two_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_in_a_write_cycle = cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave & cpu_two_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = jtag_uart_two_avalon_jtag_slave_in_a_write_cycle;

  assign wait_for_jtag_uart_two_avalon_jtag_slave_counter = 0;
  //assign jtag_uart_two_avalon_jtag_slave_irq_from_sa = jtag_uart_two_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_two_avalon_jtag_slave_irq_from_sa = jtag_uart_two_avalon_jtag_slave_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //jtag_uart_two/avalon_jtag_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module onchip_mem_one_s1_arbitrator (
                                      // inputs:
                                       clk,
                                       cpu_one_data_master_address_to_slave,
                                       cpu_one_data_master_byteenable,
                                       cpu_one_data_master_read,
                                       cpu_one_data_master_waitrequest,
                                       cpu_one_data_master_write,
                                       cpu_one_data_master_writedata,
                                       cpu_one_instruction_master_address_to_slave,
                                       cpu_one_instruction_master_latency_counter,
                                       cpu_one_instruction_master_read,
                                       onchip_mem_one_s1_readdata,
                                       reset_n,

                                      // outputs:
                                       cpu_one_data_master_granted_onchip_mem_one_s1,
                                       cpu_one_data_master_qualified_request_onchip_mem_one_s1,
                                       cpu_one_data_master_read_data_valid_onchip_mem_one_s1,
                                       cpu_one_data_master_requests_onchip_mem_one_s1,
                                       cpu_one_instruction_master_granted_onchip_mem_one_s1,
                                       cpu_one_instruction_master_qualified_request_onchip_mem_one_s1,
                                       cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1,
                                       cpu_one_instruction_master_requests_onchip_mem_one_s1,
                                       d1_onchip_mem_one_s1_end_xfer,
                                       onchip_mem_one_s1_address,
                                       onchip_mem_one_s1_byteenable,
                                       onchip_mem_one_s1_chipselect,
                                       onchip_mem_one_s1_clken,
                                       onchip_mem_one_s1_readdata_from_sa,
                                       onchip_mem_one_s1_write,
                                       onchip_mem_one_s1_writedata,
                                       registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1
                                    )
;

  output           cpu_one_data_master_granted_onchip_mem_one_s1;
  output           cpu_one_data_master_qualified_request_onchip_mem_one_s1;
  output           cpu_one_data_master_read_data_valid_onchip_mem_one_s1;
  output           cpu_one_data_master_requests_onchip_mem_one_s1;
  output           cpu_one_instruction_master_granted_onchip_mem_one_s1;
  output           cpu_one_instruction_master_qualified_request_onchip_mem_one_s1;
  output           cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1;
  output           cpu_one_instruction_master_requests_onchip_mem_one_s1;
  output           d1_onchip_mem_one_s1_end_xfer;
  output  [  9: 0] onchip_mem_one_s1_address;
  output  [  3: 0] onchip_mem_one_s1_byteenable;
  output           onchip_mem_one_s1_chipselect;
  output           onchip_mem_one_s1_clken;
  output  [ 31: 0] onchip_mem_one_s1_readdata_from_sa;
  output           onchip_mem_one_s1_write;
  output  [ 31: 0] onchip_mem_one_s1_writedata;
  output           registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1;
  input            clk;
  input   [ 19: 0] cpu_one_data_master_address_to_slave;
  input   [  3: 0] cpu_one_data_master_byteenable;
  input            cpu_one_data_master_read;
  input            cpu_one_data_master_waitrequest;
  input            cpu_one_data_master_write;
  input   [ 31: 0] cpu_one_data_master_writedata;
  input   [ 19: 0] cpu_one_instruction_master_address_to_slave;
  input            cpu_one_instruction_master_latency_counter;
  input            cpu_one_instruction_master_read;
  input   [ 31: 0] onchip_mem_one_s1_readdata;
  input            reset_n;

  wire             cpu_one_data_master_arbiterlock;
  wire             cpu_one_data_master_arbiterlock2;
  wire             cpu_one_data_master_continuerequest;
  wire             cpu_one_data_master_granted_onchip_mem_one_s1;
  wire             cpu_one_data_master_qualified_request_onchip_mem_one_s1;
  wire             cpu_one_data_master_read_data_valid_onchip_mem_one_s1;
  reg              cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register;
  wire             cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register_in;
  wire             cpu_one_data_master_requests_onchip_mem_one_s1;
  wire             cpu_one_data_master_saved_grant_onchip_mem_one_s1;
  wire             cpu_one_instruction_master_arbiterlock;
  wire             cpu_one_instruction_master_arbiterlock2;
  wire             cpu_one_instruction_master_continuerequest;
  wire             cpu_one_instruction_master_granted_onchip_mem_one_s1;
  wire             cpu_one_instruction_master_qualified_request_onchip_mem_one_s1;
  wire             cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1;
  reg              cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register;
  wire             cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register_in;
  wire             cpu_one_instruction_master_requests_onchip_mem_one_s1;
  wire             cpu_one_instruction_master_saved_grant_onchip_mem_one_s1;
  reg              d1_onchip_mem_one_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_onchip_mem_one_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_one_data_master_granted_slave_onchip_mem_one_s1;
  reg              last_cycle_cpu_one_instruction_master_granted_slave_onchip_mem_one_s1;
  wire    [  9: 0] onchip_mem_one_s1_address;
  wire             onchip_mem_one_s1_allgrants;
  wire             onchip_mem_one_s1_allow_new_arb_cycle;
  wire             onchip_mem_one_s1_any_bursting_master_saved_grant;
  wire             onchip_mem_one_s1_any_continuerequest;
  reg     [  1: 0] onchip_mem_one_s1_arb_addend;
  wire             onchip_mem_one_s1_arb_counter_enable;
  reg              onchip_mem_one_s1_arb_share_counter;
  wire             onchip_mem_one_s1_arb_share_counter_next_value;
  wire             onchip_mem_one_s1_arb_share_set_values;
  wire    [  1: 0] onchip_mem_one_s1_arb_winner;
  wire             onchip_mem_one_s1_arbitration_holdoff_internal;
  wire             onchip_mem_one_s1_beginbursttransfer_internal;
  wire             onchip_mem_one_s1_begins_xfer;
  wire    [  3: 0] onchip_mem_one_s1_byteenable;
  wire             onchip_mem_one_s1_chipselect;
  wire    [  3: 0] onchip_mem_one_s1_chosen_master_double_vector;
  wire    [  1: 0] onchip_mem_one_s1_chosen_master_rot_left;
  wire             onchip_mem_one_s1_clken;
  wire             onchip_mem_one_s1_end_xfer;
  wire             onchip_mem_one_s1_firsttransfer;
  wire    [  1: 0] onchip_mem_one_s1_grant_vector;
  wire             onchip_mem_one_s1_in_a_read_cycle;
  wire             onchip_mem_one_s1_in_a_write_cycle;
  wire    [  1: 0] onchip_mem_one_s1_master_qreq_vector;
  wire             onchip_mem_one_s1_non_bursting_master_requests;
  wire    [ 31: 0] onchip_mem_one_s1_readdata_from_sa;
  reg              onchip_mem_one_s1_reg_firsttransfer;
  reg     [  1: 0] onchip_mem_one_s1_saved_chosen_master_vector;
  reg              onchip_mem_one_s1_slavearbiterlockenable;
  wire             onchip_mem_one_s1_slavearbiterlockenable2;
  wire             onchip_mem_one_s1_unreg_firsttransfer;
  wire             onchip_mem_one_s1_waits_for_read;
  wire             onchip_mem_one_s1_waits_for_write;
  wire             onchip_mem_one_s1_write;
  wire    [ 31: 0] onchip_mem_one_s1_writedata;
  wire             p1_cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register;
  wire             p1_cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register;
  wire             registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1;
  wire    [ 19: 0] shifted_address_to_onchip_mem_one_s1_from_cpu_one_data_master;
  wire    [ 19: 0] shifted_address_to_onchip_mem_one_s1_from_cpu_one_instruction_master;
  wire             wait_for_onchip_mem_one_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~onchip_mem_one_s1_end_xfer;
    end


  assign onchip_mem_one_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_one_data_master_qualified_request_onchip_mem_one_s1 | cpu_one_instruction_master_qualified_request_onchip_mem_one_s1));
  //assign onchip_mem_one_s1_readdata_from_sa = onchip_mem_one_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign onchip_mem_one_s1_readdata_from_sa = onchip_mem_one_s1_readdata;

  assign cpu_one_data_master_requests_onchip_mem_one_s1 = ({cpu_one_data_master_address_to_slave[19 : 12] , 12'b0} == 20'h84000) & (cpu_one_data_master_read | cpu_one_data_master_write);
  //registered rdv signal_name registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1 assignment, which is an e_assign
  assign registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1 = cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register_in;

  //onchip_mem_one_s1_arb_share_counter set values, which is an e_mux
  assign onchip_mem_one_s1_arb_share_set_values = 1;

  //onchip_mem_one_s1_non_bursting_master_requests mux, which is an e_mux
  assign onchip_mem_one_s1_non_bursting_master_requests = cpu_one_data_master_requests_onchip_mem_one_s1 |
    cpu_one_instruction_master_requests_onchip_mem_one_s1 |
    cpu_one_data_master_requests_onchip_mem_one_s1 |
    cpu_one_instruction_master_requests_onchip_mem_one_s1;

  //onchip_mem_one_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign onchip_mem_one_s1_any_bursting_master_saved_grant = 0;

  //onchip_mem_one_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign onchip_mem_one_s1_arb_share_counter_next_value = onchip_mem_one_s1_firsttransfer ? (onchip_mem_one_s1_arb_share_set_values - 1) : |onchip_mem_one_s1_arb_share_counter ? (onchip_mem_one_s1_arb_share_counter - 1) : 0;

  //onchip_mem_one_s1_allgrants all slave grants, which is an e_mux
  assign onchip_mem_one_s1_allgrants = (|onchip_mem_one_s1_grant_vector) |
    (|onchip_mem_one_s1_grant_vector) |
    (|onchip_mem_one_s1_grant_vector) |
    (|onchip_mem_one_s1_grant_vector);

  //onchip_mem_one_s1_end_xfer assignment, which is an e_assign
  assign onchip_mem_one_s1_end_xfer = ~(onchip_mem_one_s1_waits_for_read | onchip_mem_one_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_onchip_mem_one_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_onchip_mem_one_s1 = onchip_mem_one_s1_end_xfer & (~onchip_mem_one_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //onchip_mem_one_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign onchip_mem_one_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_onchip_mem_one_s1 & onchip_mem_one_s1_allgrants) | (end_xfer_arb_share_counter_term_onchip_mem_one_s1 & ~onchip_mem_one_s1_non_bursting_master_requests);

  //onchip_mem_one_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_one_s1_arb_share_counter <= 0;
      else if (onchip_mem_one_s1_arb_counter_enable)
          onchip_mem_one_s1_arb_share_counter <= onchip_mem_one_s1_arb_share_counter_next_value;
    end


  //onchip_mem_one_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_one_s1_slavearbiterlockenable <= 0;
      else if ((|onchip_mem_one_s1_master_qreq_vector & end_xfer_arb_share_counter_term_onchip_mem_one_s1) | (end_xfer_arb_share_counter_term_onchip_mem_one_s1 & ~onchip_mem_one_s1_non_bursting_master_requests))
          onchip_mem_one_s1_slavearbiterlockenable <= |onchip_mem_one_s1_arb_share_counter_next_value;
    end


  //cpu_one/data_master onchip_mem_one/s1 arbiterlock, which is an e_assign
  assign cpu_one_data_master_arbiterlock = onchip_mem_one_s1_slavearbiterlockenable & cpu_one_data_master_continuerequest;

  //onchip_mem_one_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign onchip_mem_one_s1_slavearbiterlockenable2 = |onchip_mem_one_s1_arb_share_counter_next_value;

  //cpu_one/data_master onchip_mem_one/s1 arbiterlock2, which is an e_assign
  assign cpu_one_data_master_arbiterlock2 = onchip_mem_one_s1_slavearbiterlockenable2 & cpu_one_data_master_continuerequest;

  //cpu_one/instruction_master onchip_mem_one/s1 arbiterlock, which is an e_assign
  assign cpu_one_instruction_master_arbiterlock = onchip_mem_one_s1_slavearbiterlockenable & cpu_one_instruction_master_continuerequest;

  //cpu_one/instruction_master onchip_mem_one/s1 arbiterlock2, which is an e_assign
  assign cpu_one_instruction_master_arbiterlock2 = onchip_mem_one_s1_slavearbiterlockenable2 & cpu_one_instruction_master_continuerequest;

  //cpu_one/instruction_master granted onchip_mem_one/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_one_instruction_master_granted_slave_onchip_mem_one_s1 <= 0;
      else 
        last_cycle_cpu_one_instruction_master_granted_slave_onchip_mem_one_s1 <= cpu_one_instruction_master_saved_grant_onchip_mem_one_s1 ? 1 : (onchip_mem_one_s1_arbitration_holdoff_internal | ~cpu_one_instruction_master_requests_onchip_mem_one_s1) ? 0 : last_cycle_cpu_one_instruction_master_granted_slave_onchip_mem_one_s1;
    end


  //cpu_one_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_one_instruction_master_continuerequest = last_cycle_cpu_one_instruction_master_granted_slave_onchip_mem_one_s1 & cpu_one_instruction_master_requests_onchip_mem_one_s1;

  //onchip_mem_one_s1_any_continuerequest at least one master continues requesting, which is an e_mux
  assign onchip_mem_one_s1_any_continuerequest = cpu_one_instruction_master_continuerequest |
    cpu_one_data_master_continuerequest;

  assign cpu_one_data_master_qualified_request_onchip_mem_one_s1 = cpu_one_data_master_requests_onchip_mem_one_s1 & ~((cpu_one_data_master_read & ((|cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register))) | ((~cpu_one_data_master_waitrequest) & cpu_one_data_master_write) | cpu_one_instruction_master_arbiterlock);
  //cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register_in = cpu_one_data_master_granted_onchip_mem_one_s1 & cpu_one_data_master_read & ~onchip_mem_one_s1_waits_for_read & ~(|cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register);

  //shift register p1 cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register = {cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register, cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register_in};

  //cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register <= 0;
      else 
        cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register <= p1_cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register;
    end


  //local readdatavalid cpu_one_data_master_read_data_valid_onchip_mem_one_s1, which is an e_mux
  assign cpu_one_data_master_read_data_valid_onchip_mem_one_s1 = cpu_one_data_master_read_data_valid_onchip_mem_one_s1_shift_register;

  //onchip_mem_one_s1_writedata mux, which is an e_mux
  assign onchip_mem_one_s1_writedata = cpu_one_data_master_writedata;

  //mux onchip_mem_one_s1_clken, which is an e_mux
  assign onchip_mem_one_s1_clken = 1'b1;

  assign cpu_one_instruction_master_requests_onchip_mem_one_s1 = (({cpu_one_instruction_master_address_to_slave[19 : 12] , 12'b0} == 20'h84000) & (cpu_one_instruction_master_read)) & cpu_one_instruction_master_read;
  //cpu_one/data_master granted onchip_mem_one/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_one_data_master_granted_slave_onchip_mem_one_s1 <= 0;
      else 
        last_cycle_cpu_one_data_master_granted_slave_onchip_mem_one_s1 <= cpu_one_data_master_saved_grant_onchip_mem_one_s1 ? 1 : (onchip_mem_one_s1_arbitration_holdoff_internal | ~cpu_one_data_master_requests_onchip_mem_one_s1) ? 0 : last_cycle_cpu_one_data_master_granted_slave_onchip_mem_one_s1;
    end


  //cpu_one_data_master_continuerequest continued request, which is an e_mux
  assign cpu_one_data_master_continuerequest = last_cycle_cpu_one_data_master_granted_slave_onchip_mem_one_s1 & cpu_one_data_master_requests_onchip_mem_one_s1;

  assign cpu_one_instruction_master_qualified_request_onchip_mem_one_s1 = cpu_one_instruction_master_requests_onchip_mem_one_s1 & ~((cpu_one_instruction_master_read & ((1 < cpu_one_instruction_master_latency_counter))) | cpu_one_data_master_arbiterlock);
  //cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register_in = cpu_one_instruction_master_granted_onchip_mem_one_s1 & cpu_one_instruction_master_read & ~onchip_mem_one_s1_waits_for_read;

  //shift register p1 cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register = {cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register, cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register_in};

  //cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register <= 0;
      else 
        cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register <= p1_cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register;
    end


  //local readdatavalid cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1, which is an e_mux
  assign cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1 = cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1_shift_register;

  //allow new arb cycle for onchip_mem_one/s1, which is an e_assign
  assign onchip_mem_one_s1_allow_new_arb_cycle = ~cpu_one_data_master_arbiterlock & ~cpu_one_instruction_master_arbiterlock;

  //cpu_one/instruction_master assignment into master qualified-requests vector for onchip_mem_one/s1, which is an e_assign
  assign onchip_mem_one_s1_master_qreq_vector[0] = cpu_one_instruction_master_qualified_request_onchip_mem_one_s1;

  //cpu_one/instruction_master grant onchip_mem_one/s1, which is an e_assign
  assign cpu_one_instruction_master_granted_onchip_mem_one_s1 = onchip_mem_one_s1_grant_vector[0];

  //cpu_one/instruction_master saved-grant onchip_mem_one/s1, which is an e_assign
  assign cpu_one_instruction_master_saved_grant_onchip_mem_one_s1 = onchip_mem_one_s1_arb_winner[0] && cpu_one_instruction_master_requests_onchip_mem_one_s1;

  //cpu_one/data_master assignment into master qualified-requests vector for onchip_mem_one/s1, which is an e_assign
  assign onchip_mem_one_s1_master_qreq_vector[1] = cpu_one_data_master_qualified_request_onchip_mem_one_s1;

  //cpu_one/data_master grant onchip_mem_one/s1, which is an e_assign
  assign cpu_one_data_master_granted_onchip_mem_one_s1 = onchip_mem_one_s1_grant_vector[1];

  //cpu_one/data_master saved-grant onchip_mem_one/s1, which is an e_assign
  assign cpu_one_data_master_saved_grant_onchip_mem_one_s1 = onchip_mem_one_s1_arb_winner[1] && cpu_one_data_master_requests_onchip_mem_one_s1;

  //onchip_mem_one/s1 chosen-master double-vector, which is an e_assign
  assign onchip_mem_one_s1_chosen_master_double_vector = {onchip_mem_one_s1_master_qreq_vector, onchip_mem_one_s1_master_qreq_vector} & ({~onchip_mem_one_s1_master_qreq_vector, ~onchip_mem_one_s1_master_qreq_vector} + onchip_mem_one_s1_arb_addend);

  //stable onehot encoding of arb winner
  assign onchip_mem_one_s1_arb_winner = (onchip_mem_one_s1_allow_new_arb_cycle & | onchip_mem_one_s1_grant_vector) ? onchip_mem_one_s1_grant_vector : onchip_mem_one_s1_saved_chosen_master_vector;

  //saved onchip_mem_one_s1_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_one_s1_saved_chosen_master_vector <= 0;
      else if (onchip_mem_one_s1_allow_new_arb_cycle)
          onchip_mem_one_s1_saved_chosen_master_vector <= |onchip_mem_one_s1_grant_vector ? onchip_mem_one_s1_grant_vector : onchip_mem_one_s1_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign onchip_mem_one_s1_grant_vector = {(onchip_mem_one_s1_chosen_master_double_vector[1] | onchip_mem_one_s1_chosen_master_double_vector[3]),
    (onchip_mem_one_s1_chosen_master_double_vector[0] | onchip_mem_one_s1_chosen_master_double_vector[2])};

  //onchip_mem_one/s1 chosen master rotated left, which is an e_assign
  assign onchip_mem_one_s1_chosen_master_rot_left = (onchip_mem_one_s1_arb_winner << 1) ? (onchip_mem_one_s1_arb_winner << 1) : 1;

  //onchip_mem_one/s1's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_one_s1_arb_addend <= 1;
      else if (|onchip_mem_one_s1_grant_vector)
          onchip_mem_one_s1_arb_addend <= onchip_mem_one_s1_end_xfer? onchip_mem_one_s1_chosen_master_rot_left : onchip_mem_one_s1_grant_vector;
    end


  assign onchip_mem_one_s1_chipselect = cpu_one_data_master_granted_onchip_mem_one_s1 | cpu_one_instruction_master_granted_onchip_mem_one_s1;
  //onchip_mem_one_s1_firsttransfer first transaction, which is an e_assign
  assign onchip_mem_one_s1_firsttransfer = onchip_mem_one_s1_begins_xfer ? onchip_mem_one_s1_unreg_firsttransfer : onchip_mem_one_s1_reg_firsttransfer;

  //onchip_mem_one_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign onchip_mem_one_s1_unreg_firsttransfer = ~(onchip_mem_one_s1_slavearbiterlockenable & onchip_mem_one_s1_any_continuerequest);

  //onchip_mem_one_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_one_s1_reg_firsttransfer <= 1'b1;
      else if (onchip_mem_one_s1_begins_xfer)
          onchip_mem_one_s1_reg_firsttransfer <= onchip_mem_one_s1_unreg_firsttransfer;
    end


  //onchip_mem_one_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign onchip_mem_one_s1_beginbursttransfer_internal = onchip_mem_one_s1_begins_xfer;

  //onchip_mem_one_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign onchip_mem_one_s1_arbitration_holdoff_internal = onchip_mem_one_s1_begins_xfer & onchip_mem_one_s1_firsttransfer;

  //onchip_mem_one_s1_write assignment, which is an e_mux
  assign onchip_mem_one_s1_write = cpu_one_data_master_granted_onchip_mem_one_s1 & cpu_one_data_master_write;

  assign shifted_address_to_onchip_mem_one_s1_from_cpu_one_data_master = cpu_one_data_master_address_to_slave;
  //onchip_mem_one_s1_address mux, which is an e_mux
  assign onchip_mem_one_s1_address = (cpu_one_data_master_granted_onchip_mem_one_s1)? (shifted_address_to_onchip_mem_one_s1_from_cpu_one_data_master >> 2) :
    (shifted_address_to_onchip_mem_one_s1_from_cpu_one_instruction_master >> 2);

  assign shifted_address_to_onchip_mem_one_s1_from_cpu_one_instruction_master = cpu_one_instruction_master_address_to_slave;
  //d1_onchip_mem_one_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_onchip_mem_one_s1_end_xfer <= 1;
      else 
        d1_onchip_mem_one_s1_end_xfer <= onchip_mem_one_s1_end_xfer;
    end


  //onchip_mem_one_s1_waits_for_read in a cycle, which is an e_mux
  assign onchip_mem_one_s1_waits_for_read = onchip_mem_one_s1_in_a_read_cycle & 0;

  //onchip_mem_one_s1_in_a_read_cycle assignment, which is an e_assign
  assign onchip_mem_one_s1_in_a_read_cycle = (cpu_one_data_master_granted_onchip_mem_one_s1 & cpu_one_data_master_read) | (cpu_one_instruction_master_granted_onchip_mem_one_s1 & cpu_one_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = onchip_mem_one_s1_in_a_read_cycle;

  //onchip_mem_one_s1_waits_for_write in a cycle, which is an e_mux
  assign onchip_mem_one_s1_waits_for_write = onchip_mem_one_s1_in_a_write_cycle & 0;

  //onchip_mem_one_s1_in_a_write_cycle assignment, which is an e_assign
  assign onchip_mem_one_s1_in_a_write_cycle = cpu_one_data_master_granted_onchip_mem_one_s1 & cpu_one_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = onchip_mem_one_s1_in_a_write_cycle;

  assign wait_for_onchip_mem_one_s1_counter = 0;
  //onchip_mem_one_s1_byteenable byte enable port mux, which is an e_mux
  assign onchip_mem_one_s1_byteenable = (cpu_one_data_master_granted_onchip_mem_one_s1)? cpu_one_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //onchip_mem_one/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_one_data_master_granted_onchip_mem_one_s1 + cpu_one_instruction_master_granted_onchip_mem_one_s1 > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_one_data_master_saved_grant_onchip_mem_one_s1 + cpu_one_instruction_master_saved_grant_onchip_mem_one_s1 > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module onchip_mem_two_s1_arbitrator (
                                      // inputs:
                                       clk,
                                       cpu_two_data_master_address_to_slave,
                                       cpu_two_data_master_byteenable,
                                       cpu_two_data_master_read,
                                       cpu_two_data_master_waitrequest,
                                       cpu_two_data_master_write,
                                       cpu_two_data_master_writedata,
                                       cpu_two_instruction_master_address_to_slave,
                                       cpu_two_instruction_master_latency_counter,
                                       cpu_two_instruction_master_read,
                                       onchip_mem_two_s1_readdata,
                                       reset_n,

                                      // outputs:
                                       cpu_two_data_master_granted_onchip_mem_two_s1,
                                       cpu_two_data_master_qualified_request_onchip_mem_two_s1,
                                       cpu_two_data_master_read_data_valid_onchip_mem_two_s1,
                                       cpu_two_data_master_requests_onchip_mem_two_s1,
                                       cpu_two_instruction_master_granted_onchip_mem_two_s1,
                                       cpu_two_instruction_master_qualified_request_onchip_mem_two_s1,
                                       cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1,
                                       cpu_two_instruction_master_requests_onchip_mem_two_s1,
                                       d1_onchip_mem_two_s1_end_xfer,
                                       onchip_mem_two_s1_address,
                                       onchip_mem_two_s1_byteenable,
                                       onchip_mem_two_s1_chipselect,
                                       onchip_mem_two_s1_clken,
                                       onchip_mem_two_s1_readdata_from_sa,
                                       onchip_mem_two_s1_write,
                                       onchip_mem_two_s1_writedata,
                                       registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1
                                    )
;

  output           cpu_two_data_master_granted_onchip_mem_two_s1;
  output           cpu_two_data_master_qualified_request_onchip_mem_two_s1;
  output           cpu_two_data_master_read_data_valid_onchip_mem_two_s1;
  output           cpu_two_data_master_requests_onchip_mem_two_s1;
  output           cpu_two_instruction_master_granted_onchip_mem_two_s1;
  output           cpu_two_instruction_master_qualified_request_onchip_mem_two_s1;
  output           cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1;
  output           cpu_two_instruction_master_requests_onchip_mem_two_s1;
  output           d1_onchip_mem_two_s1_end_xfer;
  output  [  9: 0] onchip_mem_two_s1_address;
  output  [  3: 0] onchip_mem_two_s1_byteenable;
  output           onchip_mem_two_s1_chipselect;
  output           onchip_mem_two_s1_clken;
  output  [ 31: 0] onchip_mem_two_s1_readdata_from_sa;
  output           onchip_mem_two_s1_write;
  output  [ 31: 0] onchip_mem_two_s1_writedata;
  output           registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1;
  input            clk;
  input   [ 19: 0] cpu_two_data_master_address_to_slave;
  input   [  3: 0] cpu_two_data_master_byteenable;
  input            cpu_two_data_master_read;
  input            cpu_two_data_master_waitrequest;
  input            cpu_two_data_master_write;
  input   [ 31: 0] cpu_two_data_master_writedata;
  input   [ 19: 0] cpu_two_instruction_master_address_to_slave;
  input            cpu_two_instruction_master_latency_counter;
  input            cpu_two_instruction_master_read;
  input   [ 31: 0] onchip_mem_two_s1_readdata;
  input            reset_n;

  wire             cpu_two_data_master_arbiterlock;
  wire             cpu_two_data_master_arbiterlock2;
  wire             cpu_two_data_master_continuerequest;
  wire             cpu_two_data_master_granted_onchip_mem_two_s1;
  wire             cpu_two_data_master_qualified_request_onchip_mem_two_s1;
  wire             cpu_two_data_master_read_data_valid_onchip_mem_two_s1;
  reg              cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register;
  wire             cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register_in;
  wire             cpu_two_data_master_requests_onchip_mem_two_s1;
  wire             cpu_two_data_master_saved_grant_onchip_mem_two_s1;
  wire             cpu_two_instruction_master_arbiterlock;
  wire             cpu_two_instruction_master_arbiterlock2;
  wire             cpu_two_instruction_master_continuerequest;
  wire             cpu_two_instruction_master_granted_onchip_mem_two_s1;
  wire             cpu_two_instruction_master_qualified_request_onchip_mem_two_s1;
  wire             cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1;
  reg              cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register;
  wire             cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register_in;
  wire             cpu_two_instruction_master_requests_onchip_mem_two_s1;
  wire             cpu_two_instruction_master_saved_grant_onchip_mem_two_s1;
  reg              d1_onchip_mem_two_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_onchip_mem_two_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_two_data_master_granted_slave_onchip_mem_two_s1;
  reg              last_cycle_cpu_two_instruction_master_granted_slave_onchip_mem_two_s1;
  wire    [  9: 0] onchip_mem_two_s1_address;
  wire             onchip_mem_two_s1_allgrants;
  wire             onchip_mem_two_s1_allow_new_arb_cycle;
  wire             onchip_mem_two_s1_any_bursting_master_saved_grant;
  wire             onchip_mem_two_s1_any_continuerequest;
  reg     [  1: 0] onchip_mem_two_s1_arb_addend;
  wire             onchip_mem_two_s1_arb_counter_enable;
  reg              onchip_mem_two_s1_arb_share_counter;
  wire             onchip_mem_two_s1_arb_share_counter_next_value;
  wire             onchip_mem_two_s1_arb_share_set_values;
  wire    [  1: 0] onchip_mem_two_s1_arb_winner;
  wire             onchip_mem_two_s1_arbitration_holdoff_internal;
  wire             onchip_mem_two_s1_beginbursttransfer_internal;
  wire             onchip_mem_two_s1_begins_xfer;
  wire    [  3: 0] onchip_mem_two_s1_byteenable;
  wire             onchip_mem_two_s1_chipselect;
  wire    [  3: 0] onchip_mem_two_s1_chosen_master_double_vector;
  wire    [  1: 0] onchip_mem_two_s1_chosen_master_rot_left;
  wire             onchip_mem_two_s1_clken;
  wire             onchip_mem_two_s1_end_xfer;
  wire             onchip_mem_two_s1_firsttransfer;
  wire    [  1: 0] onchip_mem_two_s1_grant_vector;
  wire             onchip_mem_two_s1_in_a_read_cycle;
  wire             onchip_mem_two_s1_in_a_write_cycle;
  wire    [  1: 0] onchip_mem_two_s1_master_qreq_vector;
  wire             onchip_mem_two_s1_non_bursting_master_requests;
  wire    [ 31: 0] onchip_mem_two_s1_readdata_from_sa;
  reg              onchip_mem_two_s1_reg_firsttransfer;
  reg     [  1: 0] onchip_mem_two_s1_saved_chosen_master_vector;
  reg              onchip_mem_two_s1_slavearbiterlockenable;
  wire             onchip_mem_two_s1_slavearbiterlockenable2;
  wire             onchip_mem_two_s1_unreg_firsttransfer;
  wire             onchip_mem_two_s1_waits_for_read;
  wire             onchip_mem_two_s1_waits_for_write;
  wire             onchip_mem_two_s1_write;
  wire    [ 31: 0] onchip_mem_two_s1_writedata;
  wire             p1_cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register;
  wire             p1_cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register;
  wire             registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1;
  wire    [ 19: 0] shifted_address_to_onchip_mem_two_s1_from_cpu_two_data_master;
  wire    [ 19: 0] shifted_address_to_onchip_mem_two_s1_from_cpu_two_instruction_master;
  wire             wait_for_onchip_mem_two_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else 
        d1_reasons_to_wait <= ~onchip_mem_two_s1_end_xfer;
    end


  assign onchip_mem_two_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_two_data_master_qualified_request_onchip_mem_two_s1 | cpu_two_instruction_master_qualified_request_onchip_mem_two_s1));
  //assign onchip_mem_two_s1_readdata_from_sa = onchip_mem_two_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign onchip_mem_two_s1_readdata_from_sa = onchip_mem_two_s1_readdata;

  assign cpu_two_data_master_requests_onchip_mem_two_s1 = ({cpu_two_data_master_address_to_slave[19 : 12] , 12'b0} == 20'h84000) & (cpu_two_data_master_read | cpu_two_data_master_write);
  //registered rdv signal_name registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1 assignment, which is an e_assign
  assign registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1 = cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register_in;

  //onchip_mem_two_s1_arb_share_counter set values, which is an e_mux
  assign onchip_mem_two_s1_arb_share_set_values = 1;

  //onchip_mem_two_s1_non_bursting_master_requests mux, which is an e_mux
  assign onchip_mem_two_s1_non_bursting_master_requests = cpu_two_data_master_requests_onchip_mem_two_s1 |
    cpu_two_instruction_master_requests_onchip_mem_two_s1 |
    cpu_two_data_master_requests_onchip_mem_two_s1 |
    cpu_two_instruction_master_requests_onchip_mem_two_s1;

  //onchip_mem_two_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign onchip_mem_two_s1_any_bursting_master_saved_grant = 0;

  //onchip_mem_two_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign onchip_mem_two_s1_arb_share_counter_next_value = onchip_mem_two_s1_firsttransfer ? (onchip_mem_two_s1_arb_share_set_values - 1) : |onchip_mem_two_s1_arb_share_counter ? (onchip_mem_two_s1_arb_share_counter - 1) : 0;

  //onchip_mem_two_s1_allgrants all slave grants, which is an e_mux
  assign onchip_mem_two_s1_allgrants = (|onchip_mem_two_s1_grant_vector) |
    (|onchip_mem_two_s1_grant_vector) |
    (|onchip_mem_two_s1_grant_vector) |
    (|onchip_mem_two_s1_grant_vector);

  //onchip_mem_two_s1_end_xfer assignment, which is an e_assign
  assign onchip_mem_two_s1_end_xfer = ~(onchip_mem_two_s1_waits_for_read | onchip_mem_two_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_onchip_mem_two_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_onchip_mem_two_s1 = onchip_mem_two_s1_end_xfer & (~onchip_mem_two_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //onchip_mem_two_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign onchip_mem_two_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_onchip_mem_two_s1 & onchip_mem_two_s1_allgrants) | (end_xfer_arb_share_counter_term_onchip_mem_two_s1 & ~onchip_mem_two_s1_non_bursting_master_requests);

  //onchip_mem_two_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_two_s1_arb_share_counter <= 0;
      else if (onchip_mem_two_s1_arb_counter_enable)
          onchip_mem_two_s1_arb_share_counter <= onchip_mem_two_s1_arb_share_counter_next_value;
    end


  //onchip_mem_two_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_two_s1_slavearbiterlockenable <= 0;
      else if ((|onchip_mem_two_s1_master_qreq_vector & end_xfer_arb_share_counter_term_onchip_mem_two_s1) | (end_xfer_arb_share_counter_term_onchip_mem_two_s1 & ~onchip_mem_two_s1_non_bursting_master_requests))
          onchip_mem_two_s1_slavearbiterlockenable <= |onchip_mem_two_s1_arb_share_counter_next_value;
    end


  //cpu_two/data_master onchip_mem_two/s1 arbiterlock, which is an e_assign
  assign cpu_two_data_master_arbiterlock = onchip_mem_two_s1_slavearbiterlockenable & cpu_two_data_master_continuerequest;

  //onchip_mem_two_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign onchip_mem_two_s1_slavearbiterlockenable2 = |onchip_mem_two_s1_arb_share_counter_next_value;

  //cpu_two/data_master onchip_mem_two/s1 arbiterlock2, which is an e_assign
  assign cpu_two_data_master_arbiterlock2 = onchip_mem_two_s1_slavearbiterlockenable2 & cpu_two_data_master_continuerequest;

  //cpu_two/instruction_master onchip_mem_two/s1 arbiterlock, which is an e_assign
  assign cpu_two_instruction_master_arbiterlock = onchip_mem_two_s1_slavearbiterlockenable & cpu_two_instruction_master_continuerequest;

  //cpu_two/instruction_master onchip_mem_two/s1 arbiterlock2, which is an e_assign
  assign cpu_two_instruction_master_arbiterlock2 = onchip_mem_two_s1_slavearbiterlockenable2 & cpu_two_instruction_master_continuerequest;

  //cpu_two/instruction_master granted onchip_mem_two/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_two_instruction_master_granted_slave_onchip_mem_two_s1 <= 0;
      else 
        last_cycle_cpu_two_instruction_master_granted_slave_onchip_mem_two_s1 <= cpu_two_instruction_master_saved_grant_onchip_mem_two_s1 ? 1 : (onchip_mem_two_s1_arbitration_holdoff_internal | ~cpu_two_instruction_master_requests_onchip_mem_two_s1) ? 0 : last_cycle_cpu_two_instruction_master_granted_slave_onchip_mem_two_s1;
    end


  //cpu_two_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_two_instruction_master_continuerequest = last_cycle_cpu_two_instruction_master_granted_slave_onchip_mem_two_s1 & cpu_two_instruction_master_requests_onchip_mem_two_s1;

  //onchip_mem_two_s1_any_continuerequest at least one master continues requesting, which is an e_mux
  assign onchip_mem_two_s1_any_continuerequest = cpu_two_instruction_master_continuerequest |
    cpu_two_data_master_continuerequest;

  assign cpu_two_data_master_qualified_request_onchip_mem_two_s1 = cpu_two_data_master_requests_onchip_mem_two_s1 & ~((cpu_two_data_master_read & ((|cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register))) | ((~cpu_two_data_master_waitrequest) & cpu_two_data_master_write) | cpu_two_instruction_master_arbiterlock);
  //cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register_in = cpu_two_data_master_granted_onchip_mem_two_s1 & cpu_two_data_master_read & ~onchip_mem_two_s1_waits_for_read & ~(|cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register);

  //shift register p1 cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register = {cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register, cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register_in};

  //cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register <= 0;
      else 
        cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register <= p1_cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register;
    end


  //local readdatavalid cpu_two_data_master_read_data_valid_onchip_mem_two_s1, which is an e_mux
  assign cpu_two_data_master_read_data_valid_onchip_mem_two_s1 = cpu_two_data_master_read_data_valid_onchip_mem_two_s1_shift_register;

  //onchip_mem_two_s1_writedata mux, which is an e_mux
  assign onchip_mem_two_s1_writedata = cpu_two_data_master_writedata;

  //mux onchip_mem_two_s1_clken, which is an e_mux
  assign onchip_mem_two_s1_clken = 1'b1;

  assign cpu_two_instruction_master_requests_onchip_mem_two_s1 = (({cpu_two_instruction_master_address_to_slave[19 : 12] , 12'b0} == 20'h84000) & (cpu_two_instruction_master_read)) & cpu_two_instruction_master_read;
  //cpu_two/data_master granted onchip_mem_two/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_two_data_master_granted_slave_onchip_mem_two_s1 <= 0;
      else 
        last_cycle_cpu_two_data_master_granted_slave_onchip_mem_two_s1 <= cpu_two_data_master_saved_grant_onchip_mem_two_s1 ? 1 : (onchip_mem_two_s1_arbitration_holdoff_internal | ~cpu_two_data_master_requests_onchip_mem_two_s1) ? 0 : last_cycle_cpu_two_data_master_granted_slave_onchip_mem_two_s1;
    end


  //cpu_two_data_master_continuerequest continued request, which is an e_mux
  assign cpu_two_data_master_continuerequest = last_cycle_cpu_two_data_master_granted_slave_onchip_mem_two_s1 & cpu_two_data_master_requests_onchip_mem_two_s1;

  assign cpu_two_instruction_master_qualified_request_onchip_mem_two_s1 = cpu_two_instruction_master_requests_onchip_mem_two_s1 & ~((cpu_two_instruction_master_read & ((1 < cpu_two_instruction_master_latency_counter))) | cpu_two_data_master_arbiterlock);
  //cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register_in = cpu_two_instruction_master_granted_onchip_mem_two_s1 & cpu_two_instruction_master_read & ~onchip_mem_two_s1_waits_for_read;

  //shift register p1 cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register = {cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register, cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register_in};

  //cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register <= 0;
      else 
        cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register <= p1_cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register;
    end


  //local readdatavalid cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1, which is an e_mux
  assign cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1 = cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1_shift_register;

  //allow new arb cycle for onchip_mem_two/s1, which is an e_assign
  assign onchip_mem_two_s1_allow_new_arb_cycle = ~cpu_two_data_master_arbiterlock & ~cpu_two_instruction_master_arbiterlock;

  //cpu_two/instruction_master assignment into master qualified-requests vector for onchip_mem_two/s1, which is an e_assign
  assign onchip_mem_two_s1_master_qreq_vector[0] = cpu_two_instruction_master_qualified_request_onchip_mem_two_s1;

  //cpu_two/instruction_master grant onchip_mem_two/s1, which is an e_assign
  assign cpu_two_instruction_master_granted_onchip_mem_two_s1 = onchip_mem_two_s1_grant_vector[0];

  //cpu_two/instruction_master saved-grant onchip_mem_two/s1, which is an e_assign
  assign cpu_two_instruction_master_saved_grant_onchip_mem_two_s1 = onchip_mem_two_s1_arb_winner[0] && cpu_two_instruction_master_requests_onchip_mem_two_s1;

  //cpu_two/data_master assignment into master qualified-requests vector for onchip_mem_two/s1, which is an e_assign
  assign onchip_mem_two_s1_master_qreq_vector[1] = cpu_two_data_master_qualified_request_onchip_mem_two_s1;

  //cpu_two/data_master grant onchip_mem_two/s1, which is an e_assign
  assign cpu_two_data_master_granted_onchip_mem_two_s1 = onchip_mem_two_s1_grant_vector[1];

  //cpu_two/data_master saved-grant onchip_mem_two/s1, which is an e_assign
  assign cpu_two_data_master_saved_grant_onchip_mem_two_s1 = onchip_mem_two_s1_arb_winner[1] && cpu_two_data_master_requests_onchip_mem_two_s1;

  //onchip_mem_two/s1 chosen-master double-vector, which is an e_assign
  assign onchip_mem_two_s1_chosen_master_double_vector = {onchip_mem_two_s1_master_qreq_vector, onchip_mem_two_s1_master_qreq_vector} & ({~onchip_mem_two_s1_master_qreq_vector, ~onchip_mem_two_s1_master_qreq_vector} + onchip_mem_two_s1_arb_addend);

  //stable onehot encoding of arb winner
  assign onchip_mem_two_s1_arb_winner = (onchip_mem_two_s1_allow_new_arb_cycle & | onchip_mem_two_s1_grant_vector) ? onchip_mem_two_s1_grant_vector : onchip_mem_two_s1_saved_chosen_master_vector;

  //saved onchip_mem_two_s1_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_two_s1_saved_chosen_master_vector <= 0;
      else if (onchip_mem_two_s1_allow_new_arb_cycle)
          onchip_mem_two_s1_saved_chosen_master_vector <= |onchip_mem_two_s1_grant_vector ? onchip_mem_two_s1_grant_vector : onchip_mem_two_s1_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign onchip_mem_two_s1_grant_vector = {(onchip_mem_two_s1_chosen_master_double_vector[1] | onchip_mem_two_s1_chosen_master_double_vector[3]),
    (onchip_mem_two_s1_chosen_master_double_vector[0] | onchip_mem_two_s1_chosen_master_double_vector[2])};

  //onchip_mem_two/s1 chosen master rotated left, which is an e_assign
  assign onchip_mem_two_s1_chosen_master_rot_left = (onchip_mem_two_s1_arb_winner << 1) ? (onchip_mem_two_s1_arb_winner << 1) : 1;

  //onchip_mem_two/s1's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_two_s1_arb_addend <= 1;
      else if (|onchip_mem_two_s1_grant_vector)
          onchip_mem_two_s1_arb_addend <= onchip_mem_two_s1_end_xfer? onchip_mem_two_s1_chosen_master_rot_left : onchip_mem_two_s1_grant_vector;
    end


  assign onchip_mem_two_s1_chipselect = cpu_two_data_master_granted_onchip_mem_two_s1 | cpu_two_instruction_master_granted_onchip_mem_two_s1;
  //onchip_mem_two_s1_firsttransfer first transaction, which is an e_assign
  assign onchip_mem_two_s1_firsttransfer = onchip_mem_two_s1_begins_xfer ? onchip_mem_two_s1_unreg_firsttransfer : onchip_mem_two_s1_reg_firsttransfer;

  //onchip_mem_two_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign onchip_mem_two_s1_unreg_firsttransfer = ~(onchip_mem_two_s1_slavearbiterlockenable & onchip_mem_two_s1_any_continuerequest);

  //onchip_mem_two_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          onchip_mem_two_s1_reg_firsttransfer <= 1'b1;
      else if (onchip_mem_two_s1_begins_xfer)
          onchip_mem_two_s1_reg_firsttransfer <= onchip_mem_two_s1_unreg_firsttransfer;
    end


  //onchip_mem_two_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign onchip_mem_two_s1_beginbursttransfer_internal = onchip_mem_two_s1_begins_xfer;

  //onchip_mem_two_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign onchip_mem_two_s1_arbitration_holdoff_internal = onchip_mem_two_s1_begins_xfer & onchip_mem_two_s1_firsttransfer;

  //onchip_mem_two_s1_write assignment, which is an e_mux
  assign onchip_mem_two_s1_write = cpu_two_data_master_granted_onchip_mem_two_s1 & cpu_two_data_master_write;

  assign shifted_address_to_onchip_mem_two_s1_from_cpu_two_data_master = cpu_two_data_master_address_to_slave;
  //onchip_mem_two_s1_address mux, which is an e_mux
  assign onchip_mem_two_s1_address = (cpu_two_data_master_granted_onchip_mem_two_s1)? (shifted_address_to_onchip_mem_two_s1_from_cpu_two_data_master >> 2) :
    (shifted_address_to_onchip_mem_two_s1_from_cpu_two_instruction_master >> 2);

  assign shifted_address_to_onchip_mem_two_s1_from_cpu_two_instruction_master = cpu_two_instruction_master_address_to_slave;
  //d1_onchip_mem_two_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_onchip_mem_two_s1_end_xfer <= 1;
      else 
        d1_onchip_mem_two_s1_end_xfer <= onchip_mem_two_s1_end_xfer;
    end


  //onchip_mem_two_s1_waits_for_read in a cycle, which is an e_mux
  assign onchip_mem_two_s1_waits_for_read = onchip_mem_two_s1_in_a_read_cycle & 0;

  //onchip_mem_two_s1_in_a_read_cycle assignment, which is an e_assign
  assign onchip_mem_two_s1_in_a_read_cycle = (cpu_two_data_master_granted_onchip_mem_two_s1 & cpu_two_data_master_read) | (cpu_two_instruction_master_granted_onchip_mem_two_s1 & cpu_two_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = onchip_mem_two_s1_in_a_read_cycle;

  //onchip_mem_two_s1_waits_for_write in a cycle, which is an e_mux
  assign onchip_mem_two_s1_waits_for_write = onchip_mem_two_s1_in_a_write_cycle & 0;

  //onchip_mem_two_s1_in_a_write_cycle assignment, which is an e_assign
  assign onchip_mem_two_s1_in_a_write_cycle = cpu_two_data_master_granted_onchip_mem_two_s1 & cpu_two_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = onchip_mem_two_s1_in_a_write_cycle;

  assign wait_for_onchip_mem_two_s1_counter = 0;
  //onchip_mem_two_s1_byteenable byte enable port mux, which is an e_mux
  assign onchip_mem_two_s1_byteenable = (cpu_two_data_master_granted_onchip_mem_two_s1)? cpu_two_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //onchip_mem_two/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else 
        enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_two_data_master_granted_onchip_mem_two_s1 + cpu_two_instruction_master_granted_onchip_mem_two_s1 > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_two_data_master_saved_grant_onchip_mem_two_s1 + cpu_two_instruction_master_saved_grant_onchip_mem_two_s1 > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module dual_processor_system_reset_clk_domain_synch_module (
                                                             // inputs:
                                                              clk,
                                                              data_in,
                                                              reset_n,

                                                             // outputs:
                                                              data_out
                                                           )
;

  output           data_out;
  input            clk;
  input            data_in;
  input            reset_n;

  reg              data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  reg              data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_in_d1 <= 0;
      else 
        data_in_d1 <= data_in;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_out <= 0;
      else 
        data_out <= data_in_d1;
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module dual_processor_system (
                               // 1) global signals:
                                clk,
                                reset_n,

                               // the_bridge_one
                                acknowledge_to_the_bridge_one,
                                address_from_the_bridge_one,
                                bus_enable_from_the_bridge_one,
                                byte_enable_from_the_bridge_one,
                                irq_to_the_bridge_one,
                                read_data_to_the_bridge_one,
                                rw_from_the_bridge_one,
                                write_data_from_the_bridge_one,

                               // the_bridge_two
                                acknowledge_to_the_bridge_two,
                                address_from_the_bridge_two,
                                bus_enable_from_the_bridge_two,
                                byte_enable_from_the_bridge_two,
                                irq_to_the_bridge_two,
                                read_data_to_the_bridge_two,
                                rw_from_the_bridge_two,
                                write_data_from_the_bridge_two
                             )
;

  output  [ 18: 0] address_from_the_bridge_one;
  output  [ 18: 0] address_from_the_bridge_two;
  output           bus_enable_from_the_bridge_one;
  output           bus_enable_from_the_bridge_two;
  output  [  3: 0] byte_enable_from_the_bridge_one;
  output  [  3: 0] byte_enable_from_the_bridge_two;
  output           rw_from_the_bridge_one;
  output           rw_from_the_bridge_two;
  output  [ 31: 0] write_data_from_the_bridge_one;
  output  [ 31: 0] write_data_from_the_bridge_two;
  input            acknowledge_to_the_bridge_one;
  input            acknowledge_to_the_bridge_two;
  input            clk;
  input            irq_to_the_bridge_one;
  input            irq_to_the_bridge_two;
  input   [ 31: 0] read_data_to_the_bridge_one;
  input   [ 31: 0] read_data_to_the_bridge_two;
  input            reset_n;

  wire    [ 18: 0] address_from_the_bridge_one;
  wire    [ 18: 0] address_from_the_bridge_two;
  wire    [ 16: 0] bridge_one_avalon_slave_address;
  wire    [  3: 0] bridge_one_avalon_slave_byteenable;
  wire             bridge_one_avalon_slave_chipselect;
  wire             bridge_one_avalon_slave_irq;
  wire             bridge_one_avalon_slave_irq_from_sa;
  wire             bridge_one_avalon_slave_read;
  wire    [ 31: 0] bridge_one_avalon_slave_readdata;
  wire    [ 31: 0] bridge_one_avalon_slave_readdata_from_sa;
  wire             bridge_one_avalon_slave_reset;
  wire             bridge_one_avalon_slave_waitrequest;
  wire             bridge_one_avalon_slave_waitrequest_from_sa;
  wire             bridge_one_avalon_slave_write;
  wire    [ 31: 0] bridge_one_avalon_slave_writedata;
  wire    [ 16: 0] bridge_two_avalon_slave_address;
  wire    [  3: 0] bridge_two_avalon_slave_byteenable;
  wire             bridge_two_avalon_slave_chipselect;
  wire             bridge_two_avalon_slave_irq;
  wire             bridge_two_avalon_slave_irq_from_sa;
  wire             bridge_two_avalon_slave_read;
  wire    [ 31: 0] bridge_two_avalon_slave_readdata;
  wire    [ 31: 0] bridge_two_avalon_slave_readdata_from_sa;
  wire             bridge_two_avalon_slave_reset;
  wire             bridge_two_avalon_slave_waitrequest;
  wire             bridge_two_avalon_slave_waitrequest_from_sa;
  wire             bridge_two_avalon_slave_write;
  wire    [ 31: 0] bridge_two_avalon_slave_writedata;
  wire             bus_enable_from_the_bridge_one;
  wire             bus_enable_from_the_bridge_two;
  wire    [  3: 0] byte_enable_from_the_bridge_one;
  wire    [  3: 0] byte_enable_from_the_bridge_two;
  wire             clk_reset_n;
  wire    [ 19: 0] cpu_one_data_master_address;
  wire    [ 19: 0] cpu_one_data_master_address_to_slave;
  wire    [  3: 0] cpu_one_data_master_byteenable;
  wire             cpu_one_data_master_debugaccess;
  wire             cpu_one_data_master_granted_bridge_one_avalon_slave;
  wire             cpu_one_data_master_granted_cpu_one_jtag_debug_module;
  wire             cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave;
  wire             cpu_one_data_master_granted_onchip_mem_one_s1;
  wire    [ 31: 0] cpu_one_data_master_irq;
  wire             cpu_one_data_master_qualified_request_bridge_one_avalon_slave;
  wire             cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module;
  wire             cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave;
  wire             cpu_one_data_master_qualified_request_onchip_mem_one_s1;
  wire             cpu_one_data_master_read;
  wire             cpu_one_data_master_read_data_valid_bridge_one_avalon_slave;
  wire             cpu_one_data_master_read_data_valid_cpu_one_jtag_debug_module;
  wire             cpu_one_data_master_read_data_valid_jtag_uart_one_avalon_jtag_slave;
  wire             cpu_one_data_master_read_data_valid_onchip_mem_one_s1;
  wire    [ 31: 0] cpu_one_data_master_readdata;
  wire             cpu_one_data_master_requests_bridge_one_avalon_slave;
  wire             cpu_one_data_master_requests_cpu_one_jtag_debug_module;
  wire             cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave;
  wire             cpu_one_data_master_requests_onchip_mem_one_s1;
  wire             cpu_one_data_master_waitrequest;
  wire             cpu_one_data_master_write;
  wire    [ 31: 0] cpu_one_data_master_writedata;
  wire    [ 19: 0] cpu_one_instruction_master_address;
  wire    [ 19: 0] cpu_one_instruction_master_address_to_slave;
  wire             cpu_one_instruction_master_granted_cpu_one_jtag_debug_module;
  wire             cpu_one_instruction_master_granted_onchip_mem_one_s1;
  wire             cpu_one_instruction_master_latency_counter;
  wire             cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module;
  wire             cpu_one_instruction_master_qualified_request_onchip_mem_one_s1;
  wire             cpu_one_instruction_master_read;
  wire             cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module;
  wire             cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1;
  wire    [ 31: 0] cpu_one_instruction_master_readdata;
  wire             cpu_one_instruction_master_readdatavalid;
  wire             cpu_one_instruction_master_requests_cpu_one_jtag_debug_module;
  wire             cpu_one_instruction_master_requests_onchip_mem_one_s1;
  wire             cpu_one_instruction_master_waitrequest;
  wire    [  8: 0] cpu_one_jtag_debug_module_address;
  wire             cpu_one_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_one_jtag_debug_module_byteenable;
  wire             cpu_one_jtag_debug_module_chipselect;
  wire             cpu_one_jtag_debug_module_debugaccess;
  wire    [ 31: 0] cpu_one_jtag_debug_module_readdata;
  wire    [ 31: 0] cpu_one_jtag_debug_module_readdata_from_sa;
  wire             cpu_one_jtag_debug_module_reset;
  wire             cpu_one_jtag_debug_module_reset_n;
  wire             cpu_one_jtag_debug_module_resetrequest;
  wire             cpu_one_jtag_debug_module_resetrequest_from_sa;
  wire             cpu_one_jtag_debug_module_write;
  wire    [ 31: 0] cpu_one_jtag_debug_module_writedata;
  wire    [ 19: 0] cpu_two_data_master_address;
  wire    [ 19: 0] cpu_two_data_master_address_to_slave;
  wire    [  3: 0] cpu_two_data_master_byteenable;
  wire             cpu_two_data_master_debugaccess;
  wire             cpu_two_data_master_granted_bridge_two_avalon_slave;
  wire             cpu_two_data_master_granted_cpu_two_jtag_debug_module;
  wire             cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave;
  wire             cpu_two_data_master_granted_onchip_mem_two_s1;
  wire    [ 31: 0] cpu_two_data_master_irq;
  wire             cpu_two_data_master_qualified_request_bridge_two_avalon_slave;
  wire             cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module;
  wire             cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave;
  wire             cpu_two_data_master_qualified_request_onchip_mem_two_s1;
  wire             cpu_two_data_master_read;
  wire             cpu_two_data_master_read_data_valid_bridge_two_avalon_slave;
  wire             cpu_two_data_master_read_data_valid_cpu_two_jtag_debug_module;
  wire             cpu_two_data_master_read_data_valid_jtag_uart_two_avalon_jtag_slave;
  wire             cpu_two_data_master_read_data_valid_onchip_mem_two_s1;
  wire    [ 31: 0] cpu_two_data_master_readdata;
  wire             cpu_two_data_master_requests_bridge_two_avalon_slave;
  wire             cpu_two_data_master_requests_cpu_two_jtag_debug_module;
  wire             cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave;
  wire             cpu_two_data_master_requests_onchip_mem_two_s1;
  wire             cpu_two_data_master_waitrequest;
  wire             cpu_two_data_master_write;
  wire    [ 31: 0] cpu_two_data_master_writedata;
  wire    [ 19: 0] cpu_two_instruction_master_address;
  wire    [ 19: 0] cpu_two_instruction_master_address_to_slave;
  wire             cpu_two_instruction_master_granted_cpu_two_jtag_debug_module;
  wire             cpu_two_instruction_master_granted_onchip_mem_two_s1;
  wire             cpu_two_instruction_master_latency_counter;
  wire             cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module;
  wire             cpu_two_instruction_master_qualified_request_onchip_mem_two_s1;
  wire             cpu_two_instruction_master_read;
  wire             cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module;
  wire             cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1;
  wire    [ 31: 0] cpu_two_instruction_master_readdata;
  wire             cpu_two_instruction_master_readdatavalid;
  wire             cpu_two_instruction_master_requests_cpu_two_jtag_debug_module;
  wire             cpu_two_instruction_master_requests_onchip_mem_two_s1;
  wire             cpu_two_instruction_master_waitrequest;
  wire    [  8: 0] cpu_two_jtag_debug_module_address;
  wire             cpu_two_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_two_jtag_debug_module_byteenable;
  wire             cpu_two_jtag_debug_module_chipselect;
  wire             cpu_two_jtag_debug_module_debugaccess;
  wire    [ 31: 0] cpu_two_jtag_debug_module_readdata;
  wire    [ 31: 0] cpu_two_jtag_debug_module_readdata_from_sa;
  wire             cpu_two_jtag_debug_module_reset;
  wire             cpu_two_jtag_debug_module_reset_n;
  wire             cpu_two_jtag_debug_module_resetrequest;
  wire             cpu_two_jtag_debug_module_resetrequest_from_sa;
  wire             cpu_two_jtag_debug_module_write;
  wire    [ 31: 0] cpu_two_jtag_debug_module_writedata;
  wire             d1_bridge_one_avalon_slave_end_xfer;
  wire             d1_bridge_two_avalon_slave_end_xfer;
  wire             d1_cpu_one_jtag_debug_module_end_xfer;
  wire             d1_cpu_two_jtag_debug_module_end_xfer;
  wire             d1_jtag_uart_one_avalon_jtag_slave_end_xfer;
  wire             d1_jtag_uart_two_avalon_jtag_slave_end_xfer;
  wire             d1_onchip_mem_one_s1_end_xfer;
  wire             d1_onchip_mem_two_s1_end_xfer;
  wire             jtag_uart_one_avalon_jtag_slave_address;
  wire             jtag_uart_one_avalon_jtag_slave_chipselect;
  wire             jtag_uart_one_avalon_jtag_slave_dataavailable;
  wire             jtag_uart_one_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_one_avalon_jtag_slave_irq;
  wire             jtag_uart_one_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_one_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_one_avalon_jtag_slave_readdata;
  wire    [ 31: 0] jtag_uart_one_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_one_avalon_jtag_slave_readyfordata;
  wire             jtag_uart_one_avalon_jtag_slave_readyfordata_from_sa;
  wire             jtag_uart_one_avalon_jtag_slave_reset_n;
  wire             jtag_uart_one_avalon_jtag_slave_waitrequest;
  wire             jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_one_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_one_avalon_jtag_slave_writedata;
  wire             jtag_uart_two_avalon_jtag_slave_address;
  wire             jtag_uart_two_avalon_jtag_slave_chipselect;
  wire             jtag_uart_two_avalon_jtag_slave_dataavailable;
  wire             jtag_uart_two_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_two_avalon_jtag_slave_irq;
  wire             jtag_uart_two_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_two_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_two_avalon_jtag_slave_readdata;
  wire    [ 31: 0] jtag_uart_two_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_two_avalon_jtag_slave_readyfordata;
  wire             jtag_uart_two_avalon_jtag_slave_readyfordata_from_sa;
  wire             jtag_uart_two_avalon_jtag_slave_reset_n;
  wire             jtag_uart_two_avalon_jtag_slave_waitrequest;
  wire             jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_two_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_two_avalon_jtag_slave_writedata;
  wire    [  9: 0] onchip_mem_one_s1_address;
  wire    [  3: 0] onchip_mem_one_s1_byteenable;
  wire             onchip_mem_one_s1_chipselect;
  wire             onchip_mem_one_s1_clken;
  wire    [ 31: 0] onchip_mem_one_s1_readdata;
  wire    [ 31: 0] onchip_mem_one_s1_readdata_from_sa;
  wire             onchip_mem_one_s1_write;
  wire    [ 31: 0] onchip_mem_one_s1_writedata;
  wire    [  9: 0] onchip_mem_two_s1_address;
  wire    [  3: 0] onchip_mem_two_s1_byteenable;
  wire             onchip_mem_two_s1_chipselect;
  wire             onchip_mem_two_s1_clken;
  wire    [ 31: 0] onchip_mem_two_s1_readdata;
  wire    [ 31: 0] onchip_mem_two_s1_readdata_from_sa;
  wire             onchip_mem_two_s1_write;
  wire    [ 31: 0] onchip_mem_two_s1_writedata;
  wire             registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave;
  wire             registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1;
  wire             registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave;
  wire             registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1;
  wire             reset_n_sources;
  wire             rw_from_the_bridge_one;
  wire             rw_from_the_bridge_two;
  wire    [ 31: 0] write_data_from_the_bridge_one;
  wire    [ 31: 0] write_data_from_the_bridge_two;
  bridge_one_avalon_slave_arbitrator the_bridge_one_avalon_slave
    (
      .bridge_one_avalon_slave_address                                        (bridge_one_avalon_slave_address),
      .bridge_one_avalon_slave_byteenable                                     (bridge_one_avalon_slave_byteenable),
      .bridge_one_avalon_slave_chipselect                                     (bridge_one_avalon_slave_chipselect),
      .bridge_one_avalon_slave_irq                                            (bridge_one_avalon_slave_irq),
      .bridge_one_avalon_slave_irq_from_sa                                    (bridge_one_avalon_slave_irq_from_sa),
      .bridge_one_avalon_slave_read                                           (bridge_one_avalon_slave_read),
      .bridge_one_avalon_slave_readdata                                       (bridge_one_avalon_slave_readdata),
      .bridge_one_avalon_slave_readdata_from_sa                               (bridge_one_avalon_slave_readdata_from_sa),
      .bridge_one_avalon_slave_reset                                          (bridge_one_avalon_slave_reset),
      .bridge_one_avalon_slave_waitrequest                                    (bridge_one_avalon_slave_waitrequest),
      .bridge_one_avalon_slave_waitrequest_from_sa                            (bridge_one_avalon_slave_waitrequest_from_sa),
      .bridge_one_avalon_slave_write                                          (bridge_one_avalon_slave_write),
      .bridge_one_avalon_slave_writedata                                      (bridge_one_avalon_slave_writedata),
      .clk                                                                    (clk),
      .cpu_one_data_master_address_to_slave                                   (cpu_one_data_master_address_to_slave),
      .cpu_one_data_master_byteenable                                         (cpu_one_data_master_byteenable),
      .cpu_one_data_master_granted_bridge_one_avalon_slave                    (cpu_one_data_master_granted_bridge_one_avalon_slave),
      .cpu_one_data_master_qualified_request_bridge_one_avalon_slave          (cpu_one_data_master_qualified_request_bridge_one_avalon_slave),
      .cpu_one_data_master_read                                               (cpu_one_data_master_read),
      .cpu_one_data_master_read_data_valid_bridge_one_avalon_slave            (cpu_one_data_master_read_data_valid_bridge_one_avalon_slave),
      .cpu_one_data_master_requests_bridge_one_avalon_slave                   (cpu_one_data_master_requests_bridge_one_avalon_slave),
      .cpu_one_data_master_waitrequest                                        (cpu_one_data_master_waitrequest),
      .cpu_one_data_master_write                                              (cpu_one_data_master_write),
      .cpu_one_data_master_writedata                                          (cpu_one_data_master_writedata),
      .d1_bridge_one_avalon_slave_end_xfer                                    (d1_bridge_one_avalon_slave_end_xfer),
      .registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave (registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave),
      .reset_n                                                                (clk_reset_n)
    );

  bridge_one the_bridge_one
    (
      .acknowledge        (acknowledge_to_the_bridge_one),
      .address            (address_from_the_bridge_one),
      .avalon_address     (bridge_one_avalon_slave_address),
      .avalon_byteenable  (bridge_one_avalon_slave_byteenable),
      .avalon_chipselect  (bridge_one_avalon_slave_chipselect),
      .avalon_irq         (bridge_one_avalon_slave_irq),
      .avalon_read        (bridge_one_avalon_slave_read),
      .avalon_readdata    (bridge_one_avalon_slave_readdata),
      .avalon_waitrequest (bridge_one_avalon_slave_waitrequest),
      .avalon_write       (bridge_one_avalon_slave_write),
      .avalon_writedata   (bridge_one_avalon_slave_writedata),
      .bus_enable         (bus_enable_from_the_bridge_one),
      .byte_enable        (byte_enable_from_the_bridge_one),
      .clk                (clk),
      .irq                (irq_to_the_bridge_one),
      .read_data          (read_data_to_the_bridge_one),
      .reset              (bridge_one_avalon_slave_reset),
      .rw                 (rw_from_the_bridge_one),
      .write_data         (write_data_from_the_bridge_one)
    );

  bridge_two_avalon_slave_arbitrator the_bridge_two_avalon_slave
    (
      .bridge_two_avalon_slave_address                                        (bridge_two_avalon_slave_address),
      .bridge_two_avalon_slave_byteenable                                     (bridge_two_avalon_slave_byteenable),
      .bridge_two_avalon_slave_chipselect                                     (bridge_two_avalon_slave_chipselect),
      .bridge_two_avalon_slave_irq                                            (bridge_two_avalon_slave_irq),
      .bridge_two_avalon_slave_irq_from_sa                                    (bridge_two_avalon_slave_irq_from_sa),
      .bridge_two_avalon_slave_read                                           (bridge_two_avalon_slave_read),
      .bridge_two_avalon_slave_readdata                                       (bridge_two_avalon_slave_readdata),
      .bridge_two_avalon_slave_readdata_from_sa                               (bridge_two_avalon_slave_readdata_from_sa),
      .bridge_two_avalon_slave_reset                                          (bridge_two_avalon_slave_reset),
      .bridge_two_avalon_slave_waitrequest                                    (bridge_two_avalon_slave_waitrequest),
      .bridge_two_avalon_slave_waitrequest_from_sa                            (bridge_two_avalon_slave_waitrequest_from_sa),
      .bridge_two_avalon_slave_write                                          (bridge_two_avalon_slave_write),
      .bridge_two_avalon_slave_writedata                                      (bridge_two_avalon_slave_writedata),
      .clk                                                                    (clk),
      .cpu_two_data_master_address_to_slave                                   (cpu_two_data_master_address_to_slave),
      .cpu_two_data_master_byteenable                                         (cpu_two_data_master_byteenable),
      .cpu_two_data_master_granted_bridge_two_avalon_slave                    (cpu_two_data_master_granted_bridge_two_avalon_slave),
      .cpu_two_data_master_qualified_request_bridge_two_avalon_slave          (cpu_two_data_master_qualified_request_bridge_two_avalon_slave),
      .cpu_two_data_master_read                                               (cpu_two_data_master_read),
      .cpu_two_data_master_read_data_valid_bridge_two_avalon_slave            (cpu_two_data_master_read_data_valid_bridge_two_avalon_slave),
      .cpu_two_data_master_requests_bridge_two_avalon_slave                   (cpu_two_data_master_requests_bridge_two_avalon_slave),
      .cpu_two_data_master_waitrequest                                        (cpu_two_data_master_waitrequest),
      .cpu_two_data_master_write                                              (cpu_two_data_master_write),
      .cpu_two_data_master_writedata                                          (cpu_two_data_master_writedata),
      .d1_bridge_two_avalon_slave_end_xfer                                    (d1_bridge_two_avalon_slave_end_xfer),
      .registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave (registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave),
      .reset_n                                                                (clk_reset_n)
    );

  bridge_two the_bridge_two
    (
      .acknowledge        (acknowledge_to_the_bridge_two),
      .address            (address_from_the_bridge_two),
      .avalon_address     (bridge_two_avalon_slave_address),
      .avalon_byteenable  (bridge_two_avalon_slave_byteenable),
      .avalon_chipselect  (bridge_two_avalon_slave_chipselect),
      .avalon_irq         (bridge_two_avalon_slave_irq),
      .avalon_read        (bridge_two_avalon_slave_read),
      .avalon_readdata    (bridge_two_avalon_slave_readdata),
      .avalon_waitrequest (bridge_two_avalon_slave_waitrequest),
      .avalon_write       (bridge_two_avalon_slave_write),
      .avalon_writedata   (bridge_two_avalon_slave_writedata),
      .bus_enable         (bus_enable_from_the_bridge_two),
      .byte_enable        (byte_enable_from_the_bridge_two),
      .clk                (clk),
      .irq                (irq_to_the_bridge_two),
      .read_data          (read_data_to_the_bridge_two),
      .reset              (bridge_two_avalon_slave_reset),
      .rw                 (rw_from_the_bridge_two),
      .write_data         (write_data_from_the_bridge_two)
    );

  cpu_one_jtag_debug_module_arbitrator the_cpu_one_jtag_debug_module
    (
      .clk                                                                    (clk),
      .cpu_one_data_master_address_to_slave                                   (cpu_one_data_master_address_to_slave),
      .cpu_one_data_master_byteenable                                         (cpu_one_data_master_byteenable),
      .cpu_one_data_master_debugaccess                                        (cpu_one_data_master_debugaccess),
      .cpu_one_data_master_granted_cpu_one_jtag_debug_module                  (cpu_one_data_master_granted_cpu_one_jtag_debug_module),
      .cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module        (cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module),
      .cpu_one_data_master_read                                               (cpu_one_data_master_read),
      .cpu_one_data_master_read_data_valid_cpu_one_jtag_debug_module          (cpu_one_data_master_read_data_valid_cpu_one_jtag_debug_module),
      .cpu_one_data_master_requests_cpu_one_jtag_debug_module                 (cpu_one_data_master_requests_cpu_one_jtag_debug_module),
      .cpu_one_data_master_waitrequest                                        (cpu_one_data_master_waitrequest),
      .cpu_one_data_master_write                                              (cpu_one_data_master_write),
      .cpu_one_data_master_writedata                                          (cpu_one_data_master_writedata),
      .cpu_one_instruction_master_address_to_slave                            (cpu_one_instruction_master_address_to_slave),
      .cpu_one_instruction_master_granted_cpu_one_jtag_debug_module           (cpu_one_instruction_master_granted_cpu_one_jtag_debug_module),
      .cpu_one_instruction_master_latency_counter                             (cpu_one_instruction_master_latency_counter),
      .cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module (cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module),
      .cpu_one_instruction_master_read                                        (cpu_one_instruction_master_read),
      .cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module   (cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module),
      .cpu_one_instruction_master_requests_cpu_one_jtag_debug_module          (cpu_one_instruction_master_requests_cpu_one_jtag_debug_module),
      .cpu_one_jtag_debug_module_address                                      (cpu_one_jtag_debug_module_address),
      .cpu_one_jtag_debug_module_begintransfer                                (cpu_one_jtag_debug_module_begintransfer),
      .cpu_one_jtag_debug_module_byteenable                                   (cpu_one_jtag_debug_module_byteenable),
      .cpu_one_jtag_debug_module_chipselect                                   (cpu_one_jtag_debug_module_chipselect),
      .cpu_one_jtag_debug_module_debugaccess                                  (cpu_one_jtag_debug_module_debugaccess),
      .cpu_one_jtag_debug_module_readdata                                     (cpu_one_jtag_debug_module_readdata),
      .cpu_one_jtag_debug_module_readdata_from_sa                             (cpu_one_jtag_debug_module_readdata_from_sa),
      .cpu_one_jtag_debug_module_reset                                        (cpu_one_jtag_debug_module_reset),
      .cpu_one_jtag_debug_module_reset_n                                      (cpu_one_jtag_debug_module_reset_n),
      .cpu_one_jtag_debug_module_resetrequest                                 (cpu_one_jtag_debug_module_resetrequest),
      .cpu_one_jtag_debug_module_resetrequest_from_sa                         (cpu_one_jtag_debug_module_resetrequest_from_sa),
      .cpu_one_jtag_debug_module_write                                        (cpu_one_jtag_debug_module_write),
      .cpu_one_jtag_debug_module_writedata                                    (cpu_one_jtag_debug_module_writedata),
      .d1_cpu_one_jtag_debug_module_end_xfer                                  (d1_cpu_one_jtag_debug_module_end_xfer),
      .reset_n                                                                (clk_reset_n)
    );

  cpu_one_data_master_arbitrator the_cpu_one_data_master
    (
      .bridge_one_avalon_slave_irq_from_sa                                    (bridge_one_avalon_slave_irq_from_sa),
      .bridge_one_avalon_slave_readdata_from_sa                               (bridge_one_avalon_slave_readdata_from_sa),
      .bridge_one_avalon_slave_waitrequest_from_sa                            (bridge_one_avalon_slave_waitrequest_from_sa),
      .bridge_two_avalon_slave_irq_from_sa                                    (bridge_two_avalon_slave_irq_from_sa),
      .clk                                                                    (clk),
      .cpu_one_data_master_address                                            (cpu_one_data_master_address),
      .cpu_one_data_master_address_to_slave                                   (cpu_one_data_master_address_to_slave),
      .cpu_one_data_master_granted_bridge_one_avalon_slave                    (cpu_one_data_master_granted_bridge_one_avalon_slave),
      .cpu_one_data_master_granted_cpu_one_jtag_debug_module                  (cpu_one_data_master_granted_cpu_one_jtag_debug_module),
      .cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave            (cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave),
      .cpu_one_data_master_granted_onchip_mem_one_s1                          (cpu_one_data_master_granted_onchip_mem_one_s1),
      .cpu_one_data_master_irq                                                (cpu_one_data_master_irq),
      .cpu_one_data_master_qualified_request_bridge_one_avalon_slave          (cpu_one_data_master_qualified_request_bridge_one_avalon_slave),
      .cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module        (cpu_one_data_master_qualified_request_cpu_one_jtag_debug_module),
      .cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave  (cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave),
      .cpu_one_data_master_qualified_request_onchip_mem_one_s1                (cpu_one_data_master_qualified_request_onchip_mem_one_s1),
      .cpu_one_data_master_read                                               (cpu_one_data_master_read),
      .cpu_one_data_master_read_data_valid_bridge_one_avalon_slave            (cpu_one_data_master_read_data_valid_bridge_one_avalon_slave),
      .cpu_one_data_master_read_data_valid_cpu_one_jtag_debug_module          (cpu_one_data_master_read_data_valid_cpu_one_jtag_debug_module),
      .cpu_one_data_master_read_data_valid_jtag_uart_one_avalon_jtag_slave    (cpu_one_data_master_read_data_valid_jtag_uart_one_avalon_jtag_slave),
      .cpu_one_data_master_read_data_valid_onchip_mem_one_s1                  (cpu_one_data_master_read_data_valid_onchip_mem_one_s1),
      .cpu_one_data_master_readdata                                           (cpu_one_data_master_readdata),
      .cpu_one_data_master_requests_bridge_one_avalon_slave                   (cpu_one_data_master_requests_bridge_one_avalon_slave),
      .cpu_one_data_master_requests_cpu_one_jtag_debug_module                 (cpu_one_data_master_requests_cpu_one_jtag_debug_module),
      .cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave           (cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave),
      .cpu_one_data_master_requests_onchip_mem_one_s1                         (cpu_one_data_master_requests_onchip_mem_one_s1),
      .cpu_one_data_master_waitrequest                                        (cpu_one_data_master_waitrequest),
      .cpu_one_data_master_write                                              (cpu_one_data_master_write),
      .cpu_one_jtag_debug_module_readdata_from_sa                             (cpu_one_jtag_debug_module_readdata_from_sa),
      .d1_bridge_one_avalon_slave_end_xfer                                    (d1_bridge_one_avalon_slave_end_xfer),
      .d1_cpu_one_jtag_debug_module_end_xfer                                  (d1_cpu_one_jtag_debug_module_end_xfer),
      .d1_jtag_uart_one_avalon_jtag_slave_end_xfer                            (d1_jtag_uart_one_avalon_jtag_slave_end_xfer),
      .d1_onchip_mem_one_s1_end_xfer                                          (d1_onchip_mem_one_s1_end_xfer),
      .jtag_uart_one_avalon_jtag_slave_irq_from_sa                            (jtag_uart_one_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_one_avalon_jtag_slave_readdata_from_sa                       (jtag_uart_one_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa                    (jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa),
      .jtag_uart_two_avalon_jtag_slave_irq_from_sa                            (jtag_uart_two_avalon_jtag_slave_irq_from_sa),
      .onchip_mem_one_s1_readdata_from_sa                                     (onchip_mem_one_s1_readdata_from_sa),
      .registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave (registered_cpu_one_data_master_read_data_valid_bridge_one_avalon_slave),
      .registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1       (registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1),
      .reset_n                                                                (clk_reset_n)
    );

  cpu_one_instruction_master_arbitrator the_cpu_one_instruction_master
    (
      .clk                                                                    (clk),
      .cpu_one_instruction_master_address                                     (cpu_one_instruction_master_address),
      .cpu_one_instruction_master_address_to_slave                            (cpu_one_instruction_master_address_to_slave),
      .cpu_one_instruction_master_granted_cpu_one_jtag_debug_module           (cpu_one_instruction_master_granted_cpu_one_jtag_debug_module),
      .cpu_one_instruction_master_granted_onchip_mem_one_s1                   (cpu_one_instruction_master_granted_onchip_mem_one_s1),
      .cpu_one_instruction_master_latency_counter                             (cpu_one_instruction_master_latency_counter),
      .cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module (cpu_one_instruction_master_qualified_request_cpu_one_jtag_debug_module),
      .cpu_one_instruction_master_qualified_request_onchip_mem_one_s1         (cpu_one_instruction_master_qualified_request_onchip_mem_one_s1),
      .cpu_one_instruction_master_read                                        (cpu_one_instruction_master_read),
      .cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module   (cpu_one_instruction_master_read_data_valid_cpu_one_jtag_debug_module),
      .cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1           (cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1),
      .cpu_one_instruction_master_readdata                                    (cpu_one_instruction_master_readdata),
      .cpu_one_instruction_master_readdatavalid                               (cpu_one_instruction_master_readdatavalid),
      .cpu_one_instruction_master_requests_cpu_one_jtag_debug_module          (cpu_one_instruction_master_requests_cpu_one_jtag_debug_module),
      .cpu_one_instruction_master_requests_onchip_mem_one_s1                  (cpu_one_instruction_master_requests_onchip_mem_one_s1),
      .cpu_one_instruction_master_waitrequest                                 (cpu_one_instruction_master_waitrequest),
      .cpu_one_jtag_debug_module_readdata_from_sa                             (cpu_one_jtag_debug_module_readdata_from_sa),
      .d1_cpu_one_jtag_debug_module_end_xfer                                  (d1_cpu_one_jtag_debug_module_end_xfer),
      .d1_onchip_mem_one_s1_end_xfer                                          (d1_onchip_mem_one_s1_end_xfer),
      .onchip_mem_one_s1_readdata_from_sa                                     (onchip_mem_one_s1_readdata_from_sa),
      .reset_n                                                                (clk_reset_n)
    );

  cpu_one the_cpu_one
    (
      .clk                                   (clk),
      .d_address                             (cpu_one_data_master_address),
      .d_byteenable                          (cpu_one_data_master_byteenable),
      .d_irq                                 (cpu_one_data_master_irq),
      .d_read                                (cpu_one_data_master_read),
      .d_readdata                            (cpu_one_data_master_readdata),
      .d_waitrequest                         (cpu_one_data_master_waitrequest),
      .d_write                               (cpu_one_data_master_write),
      .d_writedata                           (cpu_one_data_master_writedata),
      .i_address                             (cpu_one_instruction_master_address),
      .i_read                                (cpu_one_instruction_master_read),
      .i_readdata                            (cpu_one_instruction_master_readdata),
      .i_readdatavalid                       (cpu_one_instruction_master_readdatavalid),
      .i_waitrequest                         (cpu_one_instruction_master_waitrequest),
      .jtag_debug_module_address             (cpu_one_jtag_debug_module_address),
      .jtag_debug_module_begintransfer       (cpu_one_jtag_debug_module_begintransfer),
      .jtag_debug_module_byteenable          (cpu_one_jtag_debug_module_byteenable),
      .jtag_debug_module_clk                 (clk),
      .jtag_debug_module_debugaccess         (cpu_one_jtag_debug_module_debugaccess),
      .jtag_debug_module_debugaccess_to_roms (cpu_one_data_master_debugaccess),
      .jtag_debug_module_readdata            (cpu_one_jtag_debug_module_readdata),
      .jtag_debug_module_reset               (cpu_one_jtag_debug_module_reset),
      .jtag_debug_module_resetrequest        (cpu_one_jtag_debug_module_resetrequest),
      .jtag_debug_module_select              (cpu_one_jtag_debug_module_chipselect),
      .jtag_debug_module_write               (cpu_one_jtag_debug_module_write),
      .jtag_debug_module_writedata           (cpu_one_jtag_debug_module_writedata),
      .reset_n                               (cpu_one_jtag_debug_module_reset_n)
    );

  cpu_two_jtag_debug_module_arbitrator the_cpu_two_jtag_debug_module
    (
      .clk                                                                    (clk),
      .cpu_two_data_master_address_to_slave                                   (cpu_two_data_master_address_to_slave),
      .cpu_two_data_master_byteenable                                         (cpu_two_data_master_byteenable),
      .cpu_two_data_master_debugaccess                                        (cpu_two_data_master_debugaccess),
      .cpu_two_data_master_granted_cpu_two_jtag_debug_module                  (cpu_two_data_master_granted_cpu_two_jtag_debug_module),
      .cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module        (cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module),
      .cpu_two_data_master_read                                               (cpu_two_data_master_read),
      .cpu_two_data_master_read_data_valid_cpu_two_jtag_debug_module          (cpu_two_data_master_read_data_valid_cpu_two_jtag_debug_module),
      .cpu_two_data_master_requests_cpu_two_jtag_debug_module                 (cpu_two_data_master_requests_cpu_two_jtag_debug_module),
      .cpu_two_data_master_waitrequest                                        (cpu_two_data_master_waitrequest),
      .cpu_two_data_master_write                                              (cpu_two_data_master_write),
      .cpu_two_data_master_writedata                                          (cpu_two_data_master_writedata),
      .cpu_two_instruction_master_address_to_slave                            (cpu_two_instruction_master_address_to_slave),
      .cpu_two_instruction_master_granted_cpu_two_jtag_debug_module           (cpu_two_instruction_master_granted_cpu_two_jtag_debug_module),
      .cpu_two_instruction_master_latency_counter                             (cpu_two_instruction_master_latency_counter),
      .cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module (cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module),
      .cpu_two_instruction_master_read                                        (cpu_two_instruction_master_read),
      .cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module   (cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module),
      .cpu_two_instruction_master_requests_cpu_two_jtag_debug_module          (cpu_two_instruction_master_requests_cpu_two_jtag_debug_module),
      .cpu_two_jtag_debug_module_address                                      (cpu_two_jtag_debug_module_address),
      .cpu_two_jtag_debug_module_begintransfer                                (cpu_two_jtag_debug_module_begintransfer),
      .cpu_two_jtag_debug_module_byteenable                                   (cpu_two_jtag_debug_module_byteenable),
      .cpu_two_jtag_debug_module_chipselect                                   (cpu_two_jtag_debug_module_chipselect),
      .cpu_two_jtag_debug_module_debugaccess                                  (cpu_two_jtag_debug_module_debugaccess),
      .cpu_two_jtag_debug_module_readdata                                     (cpu_two_jtag_debug_module_readdata),
      .cpu_two_jtag_debug_module_readdata_from_sa                             (cpu_two_jtag_debug_module_readdata_from_sa),
      .cpu_two_jtag_debug_module_reset                                        (cpu_two_jtag_debug_module_reset),
      .cpu_two_jtag_debug_module_reset_n                                      (cpu_two_jtag_debug_module_reset_n),
      .cpu_two_jtag_debug_module_resetrequest                                 (cpu_two_jtag_debug_module_resetrequest),
      .cpu_two_jtag_debug_module_resetrequest_from_sa                         (cpu_two_jtag_debug_module_resetrequest_from_sa),
      .cpu_two_jtag_debug_module_write                                        (cpu_two_jtag_debug_module_write),
      .cpu_two_jtag_debug_module_writedata                                    (cpu_two_jtag_debug_module_writedata),
      .d1_cpu_two_jtag_debug_module_end_xfer                                  (d1_cpu_two_jtag_debug_module_end_xfer),
      .reset_n                                                                (clk_reset_n)
    );

  cpu_two_data_master_arbitrator the_cpu_two_data_master
    (
      .bridge_one_avalon_slave_irq_from_sa                                    (bridge_one_avalon_slave_irq_from_sa),
      .bridge_two_avalon_slave_irq_from_sa                                    (bridge_two_avalon_slave_irq_from_sa),
      .bridge_two_avalon_slave_readdata_from_sa                               (bridge_two_avalon_slave_readdata_from_sa),
      .bridge_two_avalon_slave_waitrequest_from_sa                            (bridge_two_avalon_slave_waitrequest_from_sa),
      .clk                                                                    (clk),
      .cpu_two_data_master_address                                            (cpu_two_data_master_address),
      .cpu_two_data_master_address_to_slave                                   (cpu_two_data_master_address_to_slave),
      .cpu_two_data_master_granted_bridge_two_avalon_slave                    (cpu_two_data_master_granted_bridge_two_avalon_slave),
      .cpu_two_data_master_granted_cpu_two_jtag_debug_module                  (cpu_two_data_master_granted_cpu_two_jtag_debug_module),
      .cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave            (cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave),
      .cpu_two_data_master_granted_onchip_mem_two_s1                          (cpu_two_data_master_granted_onchip_mem_two_s1),
      .cpu_two_data_master_irq                                                (cpu_two_data_master_irq),
      .cpu_two_data_master_qualified_request_bridge_two_avalon_slave          (cpu_two_data_master_qualified_request_bridge_two_avalon_slave),
      .cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module        (cpu_two_data_master_qualified_request_cpu_two_jtag_debug_module),
      .cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave  (cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave),
      .cpu_two_data_master_qualified_request_onchip_mem_two_s1                (cpu_two_data_master_qualified_request_onchip_mem_two_s1),
      .cpu_two_data_master_read                                               (cpu_two_data_master_read),
      .cpu_two_data_master_read_data_valid_bridge_two_avalon_slave            (cpu_two_data_master_read_data_valid_bridge_two_avalon_slave),
      .cpu_two_data_master_read_data_valid_cpu_two_jtag_debug_module          (cpu_two_data_master_read_data_valid_cpu_two_jtag_debug_module),
      .cpu_two_data_master_read_data_valid_jtag_uart_two_avalon_jtag_slave    (cpu_two_data_master_read_data_valid_jtag_uart_two_avalon_jtag_slave),
      .cpu_two_data_master_read_data_valid_onchip_mem_two_s1                  (cpu_two_data_master_read_data_valid_onchip_mem_two_s1),
      .cpu_two_data_master_readdata                                           (cpu_two_data_master_readdata),
      .cpu_two_data_master_requests_bridge_two_avalon_slave                   (cpu_two_data_master_requests_bridge_two_avalon_slave),
      .cpu_two_data_master_requests_cpu_two_jtag_debug_module                 (cpu_two_data_master_requests_cpu_two_jtag_debug_module),
      .cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave           (cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave),
      .cpu_two_data_master_requests_onchip_mem_two_s1                         (cpu_two_data_master_requests_onchip_mem_two_s1),
      .cpu_two_data_master_waitrequest                                        (cpu_two_data_master_waitrequest),
      .cpu_two_data_master_write                                              (cpu_two_data_master_write),
      .cpu_two_jtag_debug_module_readdata_from_sa                             (cpu_two_jtag_debug_module_readdata_from_sa),
      .d1_bridge_two_avalon_slave_end_xfer                                    (d1_bridge_two_avalon_slave_end_xfer),
      .d1_cpu_two_jtag_debug_module_end_xfer                                  (d1_cpu_two_jtag_debug_module_end_xfer),
      .d1_jtag_uart_two_avalon_jtag_slave_end_xfer                            (d1_jtag_uart_two_avalon_jtag_slave_end_xfer),
      .d1_onchip_mem_two_s1_end_xfer                                          (d1_onchip_mem_two_s1_end_xfer),
      .jtag_uart_one_avalon_jtag_slave_irq_from_sa                            (jtag_uart_one_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_two_avalon_jtag_slave_irq_from_sa                            (jtag_uart_two_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_two_avalon_jtag_slave_readdata_from_sa                       (jtag_uart_two_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa                    (jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa),
      .onchip_mem_two_s1_readdata_from_sa                                     (onchip_mem_two_s1_readdata_from_sa),
      .registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave (registered_cpu_two_data_master_read_data_valid_bridge_two_avalon_slave),
      .registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1       (registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1),
      .reset_n                                                                (clk_reset_n)
    );

  cpu_two_instruction_master_arbitrator the_cpu_two_instruction_master
    (
      .clk                                                                    (clk),
      .cpu_two_instruction_master_address                                     (cpu_two_instruction_master_address),
      .cpu_two_instruction_master_address_to_slave                            (cpu_two_instruction_master_address_to_slave),
      .cpu_two_instruction_master_granted_cpu_two_jtag_debug_module           (cpu_two_instruction_master_granted_cpu_two_jtag_debug_module),
      .cpu_two_instruction_master_granted_onchip_mem_two_s1                   (cpu_two_instruction_master_granted_onchip_mem_two_s1),
      .cpu_two_instruction_master_latency_counter                             (cpu_two_instruction_master_latency_counter),
      .cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module (cpu_two_instruction_master_qualified_request_cpu_two_jtag_debug_module),
      .cpu_two_instruction_master_qualified_request_onchip_mem_two_s1         (cpu_two_instruction_master_qualified_request_onchip_mem_two_s1),
      .cpu_two_instruction_master_read                                        (cpu_two_instruction_master_read),
      .cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module   (cpu_two_instruction_master_read_data_valid_cpu_two_jtag_debug_module),
      .cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1           (cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1),
      .cpu_two_instruction_master_readdata                                    (cpu_two_instruction_master_readdata),
      .cpu_two_instruction_master_readdatavalid                               (cpu_two_instruction_master_readdatavalid),
      .cpu_two_instruction_master_requests_cpu_two_jtag_debug_module          (cpu_two_instruction_master_requests_cpu_two_jtag_debug_module),
      .cpu_two_instruction_master_requests_onchip_mem_two_s1                  (cpu_two_instruction_master_requests_onchip_mem_two_s1),
      .cpu_two_instruction_master_waitrequest                                 (cpu_two_instruction_master_waitrequest),
      .cpu_two_jtag_debug_module_readdata_from_sa                             (cpu_two_jtag_debug_module_readdata_from_sa),
      .d1_cpu_two_jtag_debug_module_end_xfer                                  (d1_cpu_two_jtag_debug_module_end_xfer),
      .d1_onchip_mem_two_s1_end_xfer                                          (d1_onchip_mem_two_s1_end_xfer),
      .onchip_mem_two_s1_readdata_from_sa                                     (onchip_mem_two_s1_readdata_from_sa),
      .reset_n                                                                (clk_reset_n)
    );

  cpu_two the_cpu_two
    (
      .clk                                   (clk),
      .d_address                             (cpu_two_data_master_address),
      .d_byteenable                          (cpu_two_data_master_byteenable),
      .d_irq                                 (cpu_two_data_master_irq),
      .d_read                                (cpu_two_data_master_read),
      .d_readdata                            (cpu_two_data_master_readdata),
      .d_waitrequest                         (cpu_two_data_master_waitrequest),
      .d_write                               (cpu_two_data_master_write),
      .d_writedata                           (cpu_two_data_master_writedata),
      .i_address                             (cpu_two_instruction_master_address),
      .i_read                                (cpu_two_instruction_master_read),
      .i_readdata                            (cpu_two_instruction_master_readdata),
      .i_readdatavalid                       (cpu_two_instruction_master_readdatavalid),
      .i_waitrequest                         (cpu_two_instruction_master_waitrequest),
      .jtag_debug_module_address             (cpu_two_jtag_debug_module_address),
      .jtag_debug_module_begintransfer       (cpu_two_jtag_debug_module_begintransfer),
      .jtag_debug_module_byteenable          (cpu_two_jtag_debug_module_byteenable),
      .jtag_debug_module_clk                 (clk),
      .jtag_debug_module_debugaccess         (cpu_two_jtag_debug_module_debugaccess),
      .jtag_debug_module_debugaccess_to_roms (cpu_two_data_master_debugaccess),
      .jtag_debug_module_readdata            (cpu_two_jtag_debug_module_readdata),
      .jtag_debug_module_reset               (cpu_two_jtag_debug_module_reset),
      .jtag_debug_module_resetrequest        (cpu_two_jtag_debug_module_resetrequest),
      .jtag_debug_module_select              (cpu_two_jtag_debug_module_chipselect),
      .jtag_debug_module_write               (cpu_two_jtag_debug_module_write),
      .jtag_debug_module_writedata           (cpu_two_jtag_debug_module_writedata),
      .reset_n                               (cpu_two_jtag_debug_module_reset_n)
    );

  jtag_uart_one_avalon_jtag_slave_arbitrator the_jtag_uart_one_avalon_jtag_slave
    (
      .clk                                                                   (clk),
      .cpu_one_data_master_address_to_slave                                  (cpu_one_data_master_address_to_slave),
      .cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave           (cpu_one_data_master_granted_jtag_uart_one_avalon_jtag_slave),
      .cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave (cpu_one_data_master_qualified_request_jtag_uart_one_avalon_jtag_slave),
      .cpu_one_data_master_read                                              (cpu_one_data_master_read),
      .cpu_one_data_master_read_data_valid_jtag_uart_one_avalon_jtag_slave   (cpu_one_data_master_read_data_valid_jtag_uart_one_avalon_jtag_slave),
      .cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave          (cpu_one_data_master_requests_jtag_uart_one_avalon_jtag_slave),
      .cpu_one_data_master_waitrequest                                       (cpu_one_data_master_waitrequest),
      .cpu_one_data_master_write                                             (cpu_one_data_master_write),
      .cpu_one_data_master_writedata                                         (cpu_one_data_master_writedata),
      .d1_jtag_uart_one_avalon_jtag_slave_end_xfer                           (d1_jtag_uart_one_avalon_jtag_slave_end_xfer),
      .jtag_uart_one_avalon_jtag_slave_address                               (jtag_uart_one_avalon_jtag_slave_address),
      .jtag_uart_one_avalon_jtag_slave_chipselect                            (jtag_uart_one_avalon_jtag_slave_chipselect),
      .jtag_uart_one_avalon_jtag_slave_dataavailable                         (jtag_uart_one_avalon_jtag_slave_dataavailable),
      .jtag_uart_one_avalon_jtag_slave_dataavailable_from_sa                 (jtag_uart_one_avalon_jtag_slave_dataavailable_from_sa),
      .jtag_uart_one_avalon_jtag_slave_irq                                   (jtag_uart_one_avalon_jtag_slave_irq),
      .jtag_uart_one_avalon_jtag_slave_irq_from_sa                           (jtag_uart_one_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_one_avalon_jtag_slave_read_n                                (jtag_uart_one_avalon_jtag_slave_read_n),
      .jtag_uart_one_avalon_jtag_slave_readdata                              (jtag_uart_one_avalon_jtag_slave_readdata),
      .jtag_uart_one_avalon_jtag_slave_readdata_from_sa                      (jtag_uart_one_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_one_avalon_jtag_slave_readyfordata                          (jtag_uart_one_avalon_jtag_slave_readyfordata),
      .jtag_uart_one_avalon_jtag_slave_readyfordata_from_sa                  (jtag_uart_one_avalon_jtag_slave_readyfordata_from_sa),
      .jtag_uart_one_avalon_jtag_slave_reset_n                               (jtag_uart_one_avalon_jtag_slave_reset_n),
      .jtag_uart_one_avalon_jtag_slave_waitrequest                           (jtag_uart_one_avalon_jtag_slave_waitrequest),
      .jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa                   (jtag_uart_one_avalon_jtag_slave_waitrequest_from_sa),
      .jtag_uart_one_avalon_jtag_slave_write_n                               (jtag_uart_one_avalon_jtag_slave_write_n),
      .jtag_uart_one_avalon_jtag_slave_writedata                             (jtag_uart_one_avalon_jtag_slave_writedata),
      .reset_n                                                               (clk_reset_n)
    );

  jtag_uart_one the_jtag_uart_one
    (
      .av_address     (jtag_uart_one_avalon_jtag_slave_address),
      .av_chipselect  (jtag_uart_one_avalon_jtag_slave_chipselect),
      .av_irq         (jtag_uart_one_avalon_jtag_slave_irq),
      .av_read_n      (jtag_uart_one_avalon_jtag_slave_read_n),
      .av_readdata    (jtag_uart_one_avalon_jtag_slave_readdata),
      .av_waitrequest (jtag_uart_one_avalon_jtag_slave_waitrequest),
      .av_write_n     (jtag_uart_one_avalon_jtag_slave_write_n),
      .av_writedata   (jtag_uart_one_avalon_jtag_slave_writedata),
      .clk            (clk),
      .dataavailable  (jtag_uart_one_avalon_jtag_slave_dataavailable),
      .readyfordata   (jtag_uart_one_avalon_jtag_slave_readyfordata),
      .rst_n          (jtag_uart_one_avalon_jtag_slave_reset_n)
    );

  jtag_uart_two_avalon_jtag_slave_arbitrator the_jtag_uart_two_avalon_jtag_slave
    (
      .clk                                                                   (clk),
      .cpu_two_data_master_address_to_slave                                  (cpu_two_data_master_address_to_slave),
      .cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave           (cpu_two_data_master_granted_jtag_uart_two_avalon_jtag_slave),
      .cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave (cpu_two_data_master_qualified_request_jtag_uart_two_avalon_jtag_slave),
      .cpu_two_data_master_read                                              (cpu_two_data_master_read),
      .cpu_two_data_master_read_data_valid_jtag_uart_two_avalon_jtag_slave   (cpu_two_data_master_read_data_valid_jtag_uart_two_avalon_jtag_slave),
      .cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave          (cpu_two_data_master_requests_jtag_uart_two_avalon_jtag_slave),
      .cpu_two_data_master_waitrequest                                       (cpu_two_data_master_waitrequest),
      .cpu_two_data_master_write                                             (cpu_two_data_master_write),
      .cpu_two_data_master_writedata                                         (cpu_two_data_master_writedata),
      .d1_jtag_uart_two_avalon_jtag_slave_end_xfer                           (d1_jtag_uart_two_avalon_jtag_slave_end_xfer),
      .jtag_uart_two_avalon_jtag_slave_address                               (jtag_uart_two_avalon_jtag_slave_address),
      .jtag_uart_two_avalon_jtag_slave_chipselect                            (jtag_uart_two_avalon_jtag_slave_chipselect),
      .jtag_uart_two_avalon_jtag_slave_dataavailable                         (jtag_uart_two_avalon_jtag_slave_dataavailable),
      .jtag_uart_two_avalon_jtag_slave_dataavailable_from_sa                 (jtag_uart_two_avalon_jtag_slave_dataavailable_from_sa),
      .jtag_uart_two_avalon_jtag_slave_irq                                   (jtag_uart_two_avalon_jtag_slave_irq),
      .jtag_uart_two_avalon_jtag_slave_irq_from_sa                           (jtag_uart_two_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_two_avalon_jtag_slave_read_n                                (jtag_uart_two_avalon_jtag_slave_read_n),
      .jtag_uart_two_avalon_jtag_slave_readdata                              (jtag_uart_two_avalon_jtag_slave_readdata),
      .jtag_uart_two_avalon_jtag_slave_readdata_from_sa                      (jtag_uart_two_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_two_avalon_jtag_slave_readyfordata                          (jtag_uart_two_avalon_jtag_slave_readyfordata),
      .jtag_uart_two_avalon_jtag_slave_readyfordata_from_sa                  (jtag_uart_two_avalon_jtag_slave_readyfordata_from_sa),
      .jtag_uart_two_avalon_jtag_slave_reset_n                               (jtag_uart_two_avalon_jtag_slave_reset_n),
      .jtag_uart_two_avalon_jtag_slave_waitrequest                           (jtag_uart_two_avalon_jtag_slave_waitrequest),
      .jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa                   (jtag_uart_two_avalon_jtag_slave_waitrequest_from_sa),
      .jtag_uart_two_avalon_jtag_slave_write_n                               (jtag_uart_two_avalon_jtag_slave_write_n),
      .jtag_uart_two_avalon_jtag_slave_writedata                             (jtag_uart_two_avalon_jtag_slave_writedata),
      .reset_n                                                               (clk_reset_n)
    );

  jtag_uart_two the_jtag_uart_two
    (
      .av_address     (jtag_uart_two_avalon_jtag_slave_address),
      .av_chipselect  (jtag_uart_two_avalon_jtag_slave_chipselect),
      .av_irq         (jtag_uart_two_avalon_jtag_slave_irq),
      .av_read_n      (jtag_uart_two_avalon_jtag_slave_read_n),
      .av_readdata    (jtag_uart_two_avalon_jtag_slave_readdata),
      .av_waitrequest (jtag_uart_two_avalon_jtag_slave_waitrequest),
      .av_write_n     (jtag_uart_two_avalon_jtag_slave_write_n),
      .av_writedata   (jtag_uart_two_avalon_jtag_slave_writedata),
      .clk            (clk),
      .dataavailable  (jtag_uart_two_avalon_jtag_slave_dataavailable),
      .readyfordata   (jtag_uart_two_avalon_jtag_slave_readyfordata),
      .rst_n          (jtag_uart_two_avalon_jtag_slave_reset_n)
    );

  onchip_mem_one_s1_arbitrator the_onchip_mem_one_s1
    (
      .clk                                                              (clk),
      .cpu_one_data_master_address_to_slave                             (cpu_one_data_master_address_to_slave),
      .cpu_one_data_master_byteenable                                   (cpu_one_data_master_byteenable),
      .cpu_one_data_master_granted_onchip_mem_one_s1                    (cpu_one_data_master_granted_onchip_mem_one_s1),
      .cpu_one_data_master_qualified_request_onchip_mem_one_s1          (cpu_one_data_master_qualified_request_onchip_mem_one_s1),
      .cpu_one_data_master_read                                         (cpu_one_data_master_read),
      .cpu_one_data_master_read_data_valid_onchip_mem_one_s1            (cpu_one_data_master_read_data_valid_onchip_mem_one_s1),
      .cpu_one_data_master_requests_onchip_mem_one_s1                   (cpu_one_data_master_requests_onchip_mem_one_s1),
      .cpu_one_data_master_waitrequest                                  (cpu_one_data_master_waitrequest),
      .cpu_one_data_master_write                                        (cpu_one_data_master_write),
      .cpu_one_data_master_writedata                                    (cpu_one_data_master_writedata),
      .cpu_one_instruction_master_address_to_slave                      (cpu_one_instruction_master_address_to_slave),
      .cpu_one_instruction_master_granted_onchip_mem_one_s1             (cpu_one_instruction_master_granted_onchip_mem_one_s1),
      .cpu_one_instruction_master_latency_counter                       (cpu_one_instruction_master_latency_counter),
      .cpu_one_instruction_master_qualified_request_onchip_mem_one_s1   (cpu_one_instruction_master_qualified_request_onchip_mem_one_s1),
      .cpu_one_instruction_master_read                                  (cpu_one_instruction_master_read),
      .cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1     (cpu_one_instruction_master_read_data_valid_onchip_mem_one_s1),
      .cpu_one_instruction_master_requests_onchip_mem_one_s1            (cpu_one_instruction_master_requests_onchip_mem_one_s1),
      .d1_onchip_mem_one_s1_end_xfer                                    (d1_onchip_mem_one_s1_end_xfer),
      .onchip_mem_one_s1_address                                        (onchip_mem_one_s1_address),
      .onchip_mem_one_s1_byteenable                                     (onchip_mem_one_s1_byteenable),
      .onchip_mem_one_s1_chipselect                                     (onchip_mem_one_s1_chipselect),
      .onchip_mem_one_s1_clken                                          (onchip_mem_one_s1_clken),
      .onchip_mem_one_s1_readdata                                       (onchip_mem_one_s1_readdata),
      .onchip_mem_one_s1_readdata_from_sa                               (onchip_mem_one_s1_readdata_from_sa),
      .onchip_mem_one_s1_write                                          (onchip_mem_one_s1_write),
      .onchip_mem_one_s1_writedata                                      (onchip_mem_one_s1_writedata),
      .registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1 (registered_cpu_one_data_master_read_data_valid_onchip_mem_one_s1),
      .reset_n                                                          (clk_reset_n)
    );

  onchip_mem_one the_onchip_mem_one
    (
      .address    (onchip_mem_one_s1_address),
      .byteenable (onchip_mem_one_s1_byteenable),
      .chipselect (onchip_mem_one_s1_chipselect),
      .clk        (clk),
      .clken      (onchip_mem_one_s1_clken),
      .readdata   (onchip_mem_one_s1_readdata),
      .write      (onchip_mem_one_s1_write),
      .writedata  (onchip_mem_one_s1_writedata)
    );

  onchip_mem_two_s1_arbitrator the_onchip_mem_two_s1
    (
      .clk                                                              (clk),
      .cpu_two_data_master_address_to_slave                             (cpu_two_data_master_address_to_slave),
      .cpu_two_data_master_byteenable                                   (cpu_two_data_master_byteenable),
      .cpu_two_data_master_granted_onchip_mem_two_s1                    (cpu_two_data_master_granted_onchip_mem_two_s1),
      .cpu_two_data_master_qualified_request_onchip_mem_two_s1          (cpu_two_data_master_qualified_request_onchip_mem_two_s1),
      .cpu_two_data_master_read                                         (cpu_two_data_master_read),
      .cpu_two_data_master_read_data_valid_onchip_mem_two_s1            (cpu_two_data_master_read_data_valid_onchip_mem_two_s1),
      .cpu_two_data_master_requests_onchip_mem_two_s1                   (cpu_two_data_master_requests_onchip_mem_two_s1),
      .cpu_two_data_master_waitrequest                                  (cpu_two_data_master_waitrequest),
      .cpu_two_data_master_write                                        (cpu_two_data_master_write),
      .cpu_two_data_master_writedata                                    (cpu_two_data_master_writedata),
      .cpu_two_instruction_master_address_to_slave                      (cpu_two_instruction_master_address_to_slave),
      .cpu_two_instruction_master_granted_onchip_mem_two_s1             (cpu_two_instruction_master_granted_onchip_mem_two_s1),
      .cpu_two_instruction_master_latency_counter                       (cpu_two_instruction_master_latency_counter),
      .cpu_two_instruction_master_qualified_request_onchip_mem_two_s1   (cpu_two_instruction_master_qualified_request_onchip_mem_two_s1),
      .cpu_two_instruction_master_read                                  (cpu_two_instruction_master_read),
      .cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1     (cpu_two_instruction_master_read_data_valid_onchip_mem_two_s1),
      .cpu_two_instruction_master_requests_onchip_mem_two_s1            (cpu_two_instruction_master_requests_onchip_mem_two_s1),
      .d1_onchip_mem_two_s1_end_xfer                                    (d1_onchip_mem_two_s1_end_xfer),
      .onchip_mem_two_s1_address                                        (onchip_mem_two_s1_address),
      .onchip_mem_two_s1_byteenable                                     (onchip_mem_two_s1_byteenable),
      .onchip_mem_two_s1_chipselect                                     (onchip_mem_two_s1_chipselect),
      .onchip_mem_two_s1_clken                                          (onchip_mem_two_s1_clken),
      .onchip_mem_two_s1_readdata                                       (onchip_mem_two_s1_readdata),
      .onchip_mem_two_s1_readdata_from_sa                               (onchip_mem_two_s1_readdata_from_sa),
      .onchip_mem_two_s1_write                                          (onchip_mem_two_s1_write),
      .onchip_mem_two_s1_writedata                                      (onchip_mem_two_s1_writedata),
      .registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1 (registered_cpu_two_data_master_read_data_valid_onchip_mem_two_s1),
      .reset_n                                                          (clk_reset_n)
    );

  onchip_mem_two the_onchip_mem_two
    (
      .address    (onchip_mem_two_s1_address),
      .byteenable (onchip_mem_two_s1_byteenable),
      .chipselect (onchip_mem_two_s1_chipselect),
      .clk        (clk),
      .clken      (onchip_mem_two_s1_clken),
      .readdata   (onchip_mem_two_s1_readdata),
      .write      (onchip_mem_two_s1_write),
      .writedata  (onchip_mem_two_s1_writedata)
    );

  //reset is asserted asynchronously and deasserted synchronously
  dual_processor_system_reset_clk_domain_synch_module dual_processor_system_reset_clk_domain_synch
    (
      .clk      (clk),
      .data_in  (1'b1),
      .data_out (clk_reset_n),
      .reset_n  (reset_n_sources)
    );

  //reset sources mux, which is an e_mux
  assign reset_n_sources = ~(~reset_n |
    0 |
    cpu_one_jtag_debug_module_resetrequest_from_sa |
    cpu_one_jtag_debug_module_resetrequest_from_sa |
    cpu_two_jtag_debug_module_resetrequest_from_sa |
    cpu_two_jtag_debug_module_resetrequest_from_sa);


endmodule


//synthesis translate_off



// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

// AND HERE WILL BE PRESERVED </ALTERA_NOTE>


// If user logic components use Altsync_Ram with convert_hex2ver.dll,
// set USE_convert_hex2ver in the user comments section above

// `ifdef USE_convert_hex2ver
// `else
// `define NO_PLI 1
// `endif

`include "c:/altera/90/quartus/eda/sim_lib/altera_mf.v"
`include "c:/altera/90/quartus/eda/sim_lib/220model.v"
`include "c:/altera/90/quartus/eda/sim_lib/sgate.v"
`include "bridge_one.v"
`include "bridge_two.v"
`include "cpu_two_test_bench.v"
`include "cpu_two_mult_cell.v"
`include "cpu_two_oci_test_bench.v"
`include "cpu_two_jtag_debug_module_tck.v"
`include "cpu_two_jtag_debug_module_sysclk.v"
`include "cpu_two_jtag_debug_module_wrapper.v"
`include "cpu_two.v"
`include "cpu_one_test_bench.v"
`include "cpu_one_mult_cell.v"
`include "cpu_one_oci_test_bench.v"
`include "cpu_one_jtag_debug_module_tck.v"
`include "cpu_one_jtag_debug_module_sysclk.v"
`include "cpu_one_jtag_debug_module_wrapper.v"
`include "cpu_one.v"
`include "onchip_mem_two.v"
`include "jtag_uart_one.v"
`include "jtag_uart_two.v"
`include "onchip_mem_one.v"

`timescale 1ns / 1ps

module test_bench 
;


  wire             acknowledge_to_the_bridge_one;
  wire             acknowledge_to_the_bridge_two;
  wire    [ 18: 0] address_from_the_bridge_one;
  wire    [ 18: 0] address_from_the_bridge_two;
  wire             bus_enable_from_the_bridge_one;
  wire             bus_enable_from_the_bridge_two;
  wire    [  3: 0] byte_enable_from_the_bridge_one;
  wire    [  3: 0] byte_enable_from_the_bridge_two;
  reg              clk;
  wire             irq_to_the_bridge_one;
  wire             irq_to_the_bridge_two;
  wire             jtag_uart_one_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_one_avalon_jtag_slave_readyfordata_from_sa;
  wire             jtag_uart_two_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_two_avalon_jtag_slave_readyfordata_from_sa;
  wire    [ 31: 0] read_data_to_the_bridge_one;
  wire    [ 31: 0] read_data_to_the_bridge_two;
  reg              reset_n;
  wire             rw_from_the_bridge_one;
  wire             rw_from_the_bridge_two;
  wire    [ 31: 0] write_data_from_the_bridge_one;
  wire    [ 31: 0] write_data_from_the_bridge_two;


// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
//  add your signals and additional architecture here
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>

  //Set us up the Dut
  dual_processor_system DUT
    (
      .acknowledge_to_the_bridge_one   (acknowledge_to_the_bridge_one),
      .acknowledge_to_the_bridge_two   (acknowledge_to_the_bridge_two),
      .address_from_the_bridge_one     (address_from_the_bridge_one),
      .address_from_the_bridge_two     (address_from_the_bridge_two),
      .bus_enable_from_the_bridge_one  (bus_enable_from_the_bridge_one),
      .bus_enable_from_the_bridge_two  (bus_enable_from_the_bridge_two),
      .byte_enable_from_the_bridge_one (byte_enable_from_the_bridge_one),
      .byte_enable_from_the_bridge_two (byte_enable_from_the_bridge_two),
      .clk                             (clk),
      .irq_to_the_bridge_one           (irq_to_the_bridge_one),
      .irq_to_the_bridge_two           (irq_to_the_bridge_two),
      .read_data_to_the_bridge_one     (read_data_to_the_bridge_one),
      .read_data_to_the_bridge_two     (read_data_to_the_bridge_two),
      .reset_n                         (reset_n),
      .rw_from_the_bridge_one          (rw_from_the_bridge_one),
      .rw_from_the_bridge_two          (rw_from_the_bridge_two),
      .write_data_from_the_bridge_one  (write_data_from_the_bridge_one),
      .write_data_from_the_bridge_two  (write_data_from_the_bridge_two)
    );

  initial
    clk = 1'b0;
  always
    #10 clk <= ~clk;
  
  initial 
    begin
      reset_n <= 0;
      #200 reset_n <= 1;
    end

endmodule


//synthesis translate_on