Analysis & Synthesis report for signaltap
Mon Jul 20 16:27:13 2009
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |signaltap|ps
  9. Registers Removed During Synthesis
 10. General Register Statistics
 11. Inverted Register Statistics
 12. Multiplexer Restructuring Statistics (Restructuring Performed)
 13. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body
 14. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst
 15. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_hps3:auto_generated
 16. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:\adv_point_3_and_more:advance_pointer_counter
 17. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:read_pointer_counter
 18. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_advance_pointer_counter
 19. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_read_pointer_counter
 20. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr
 21. Source assignments for sld_hub:sld_hub_inst
 22. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg
 23. Parameter Settings for User Entity Instance: Top-level Entity: |signaltap
 24. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 25. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 26. SignalTap II Logic Analyzer Settings
 27. Connections to In-System Debugging Instance "auto_signaltap_0"
 28. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                      ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Mon Jul 20 16:27:13 2009        ;
; Quartus II Version                 ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name                      ; signaltap                                    ;
; Top-level Entity Name              ; signaltap                                    ;
; Family                             ; Cyclone II                                   ;
; Total logic elements               ; 603                                          ;
;     Total combinational functions  ; 360                                          ;
;     Dedicated logic registers      ; 462                                          ;
; Total registers                    ; 462                                          ;
; Total pins                         ; 11                                           ;
; Total virtual pins                 ; 0                                            ;
; Total memory bits                  ; 1,792                                        ;
; Embedded Multiplier 9-bit elements ; 0                                            ;
; Total PLLs                         ; 0                                            ;
+------------------------------------+----------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option                                                       ; Setting            ; Default Value      ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device                                                       ; EP2C20F484C7       ;                    ;
; Top-level entity name                                        ; signaltap          ; signaltap          ;
; Family name                                                  ; Cyclone II         ; Stratix II         ;
; Optimization Technique                                       ; Speed              ; Balanced           ;
; Use Generated Physical Constraints File                      ; Off                ;                    ;
; Use smart compilation                                        ; Off                ; Off                ;
; Restructure Multiplexers                                     ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                          ; Off                ; Off                ;
; Preserve fewer node names                                    ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                    ; Off                ; Off                ;
; Verilog Version                                              ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                 ; VHDL93             ; VHDL93             ;
; State Machine Processing                                     ; Auto               ; Auto               ;
; Safe State Machine                                           ; Off                ; Off                ;
; Extract Verilog State Machines                               ; On                 ; On                 ;
; Extract VHDL State Machines                                  ; On                 ; On                 ;
; Ignore Verilog initial constructs                            ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                   ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops               ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                      ; On                 ; On                 ;
; Parallel Synthesis                                           ; Off                ; Off                ;
; DSP Block Balancing                                          ; Auto               ; Auto               ;
; NOT Gate Push-Back                                           ; On                 ; On                 ;
; Power-Up Don't Care                                          ; On                 ; On                 ;
; Remove Redundant Logic Cells                                 ; Off                ; Off                ;
; Remove Duplicate Registers                                   ; On                 ; On                 ;
; Ignore CARRY Buffers                                         ; Off                ; Off                ;
; Ignore CASCADE Buffers                                       ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                        ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                    ; Off                ; Off                ;
; Ignore LCELL Buffers                                         ; Off                ; Off                ;
; Ignore SOFT Buffers                                          ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                               ; Off                ; Off                ;
; Carry Chain Length                                           ; 70                 ; 70                 ;
; Auto Carry Chains                                            ; On                 ; On                 ;
; Auto Open-Drain Pins                                         ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                        ; Off                ; Off                ;
; Auto ROM Replacement                                         ; On                 ; On                 ;
; Auto RAM Replacement                                         ; On                 ; On                 ;
; Auto Shift Register Replacement                              ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                ; On                 ; On                 ;
; Strict RAM Replacement                                       ; Off                ; Off                ;
; Allow Synchronous Control Signals                            ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                       ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                            ; Off                ; Off                ;
; Auto Resource Sharing                                        ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                           ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                           ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing          ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives            ; Off                ; Off                ;
; Timing-Driven Synthesis                                      ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report           ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                           ; Off                ; Off                ;
; Synchronization Register Chain Length                        ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                 ; Normal compilation ; Normal compilation ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Auto Gated Clock Conversion                                  ; Off                ; Off                ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
; Analysis & Synthesis Message Level                           ; Medium             ; Medium             ;
+--------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                        ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                              ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------+
; signaltap.v                      ; yes             ; User Verilog HDL File        ; D:/Course/Digital Logic/signaltap/signaltap.v                             ;
; sld_signaltap.vhd                ; yes             ; Encrypted Megafunction       ; c:/altera/90/quartus/libraries/megafunctions/sld_signaltap.vhd            ;
; sld_ela_control.vhd              ; yes             ; Encrypted Megafunction       ; c:/altera/90/quartus/libraries/megafunctions/sld_ela_control.vhd          ;
; LPM_SHIFTREG.tdf                 ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf             ;
; lpm_constant.inc                 ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/lpm_constant.inc             ;
; dffeea.inc                       ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/dffeea.inc                   ;
; aglobal90.inc                    ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/aglobal90.inc                ;
; sld_mbpmg.vhd                    ; yes             ; Encrypted Megafunction       ; c:/altera/90/quartus/libraries/megafunctions/sld_mbpmg.vhd                ;
; sld_ela_trigger_flow_mgr.vhd     ; yes             ; Encrypted Megafunction       ; c:/altera/90/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd ;
; sld_buffer_manager.vhd           ; yes             ; Encrypted Megafunction       ; c:/altera/90/quartus/libraries/megafunctions/sld_buffer_manager.vhd       ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/altsyncram.tdf               ;
; stratix_ram_block.inc            ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/stratix_ram_block.inc        ;
; lpm_mux.inc                      ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/lpm_mux.inc                  ;
; lpm_decode.inc                   ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/lpm_decode.inc               ;
; a_rdenreg.inc                    ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/a_rdenreg.inc                ;
; altrom.inc                       ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/altrom.inc                   ;
; altram.inc                       ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/altram.inc                   ;
; altdpram.inc                     ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/altdpram.inc                 ;
; altqpram.inc                     ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/altqpram.inc                 ;
; db/altsyncram_hps3.tdf           ; yes             ; Auto-Generated Megafunction  ; D:/Course/Digital Logic/signaltap/db/altsyncram_hps3.tdf                  ;
; altdpram.tdf                     ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/altdpram.tdf                 ;
; memmodes.inc                     ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/others/maxplus2/memmodes.inc               ;
; a_hdffe.inc                      ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/a_hdffe.inc                  ;
; alt_le_rden_reg.inc              ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/alt_le_rden_reg.inc          ;
; altsyncram.inc                   ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/altsyncram.inc               ;
; lpm_mux.tdf                      ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/lpm_mux.tdf                  ;
; muxlut.inc                       ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/muxlut.inc                   ;
; bypassff.inc                     ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/bypassff.inc                 ;
; altshift.inc                     ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/altshift.inc                 ;
; db/mux_aoc.tdf                   ; yes             ; Auto-Generated Megafunction  ; D:/Course/Digital Logic/signaltap/db/mux_aoc.tdf                          ;
; lpm_decode.tdf                   ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/lpm_decode.tdf               ;
; declut.inc                       ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/declut.inc                   ;
; lpm_compare.inc                  ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/lpm_compare.inc              ;
; db/decode_rqf.tdf                ; yes             ; Auto-Generated Megafunction  ; D:/Course/Digital Logic/signaltap/db/decode_rqf.tdf                       ;
; LPM_COUNTER.tdf                  ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/LPM_COUNTER.tdf              ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/lpm_add_sub.inc              ;
; cmpconst.inc                     ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/cmpconst.inc                 ;
; lpm_counter.inc                  ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/lpm_counter.inc              ;
; alt_synch_counter.inc            ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/alt_synch_counter.inc        ;
; alt_synch_counter_f.inc          ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/alt_synch_counter_f.inc      ;
; alt_counter_f10ke.inc            ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/alt_counter_f10ke.inc        ;
; alt_counter_stratix.inc          ; yes             ; Megafunction                 ; c:/altera/90/quartus/libraries/megafunctions/alt_counter_stratix.inc      ;
; db/cntr_rbi.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/Course/Digital Logic/signaltap/db/cntr_rbi.tdf                         ;
; db/cmpr_8cc.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/Course/Digital Logic/signaltap/db/cmpr_8cc.tdf                         ;
; db/cntr_02j.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/Course/Digital Logic/signaltap/db/cntr_02j.tdf                         ;
; db/cntr_sbi.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/Course/Digital Logic/signaltap/db/cntr_sbi.tdf                         ;
; db/cntr_gui.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/Course/Digital Logic/signaltap/db/cntr_gui.tdf                         ;
; db/cmpr_5cc.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/Course/Digital Logic/signaltap/db/cmpr_5cc.tdf                         ;
; sld_rom_sr.vhd                   ; yes             ; Encrypted Megafunction       ; c:/altera/90/quartus/libraries/megafunctions/sld_rom_sr.vhd               ;
; sld_hub.vhd                      ; yes             ; Encrypted Megafunction       ; c:/altera/90/quartus/libraries/megafunctions/sld_hub.vhd                  ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------+


+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                            ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Estimated Total logic elements              ; 603                      ;
;                                             ;                          ;
; Total combinational functions               ; 360                      ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 185                      ;
;     -- 3 input functions                    ; 93                       ;
;     -- <=2 input functions                  ; 82                       ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 322                      ;
;     -- arithmetic mode                      ; 38                       ;
;                                             ;                          ;
; Total registers                             ; 462                      ;
;     -- Dedicated logic registers            ; 462                      ;
;     -- I/O registers                        ; 0                        ;
;                                             ;                          ;
; I/O pins                                    ; 11                       ;
; Total memory bits                           ; 1792                     ;
; Maximum fan-out node                        ; altera_internal_jtag~TDO ;
; Maximum fan-out                             ; 277                      ;
; Total fan-out                               ; 2843                     ;
; Average fan-out                             ; 3.34                     ;
+---------------------------------------------+--------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                           ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                                                                      ; Library Name ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |signaltap                                                                                           ; 360 (8)           ; 462 (11)     ; 1792        ; 0            ; 0       ; 0         ; 11   ; 0            ; |signaltap                                                                                                                                                                                                                                                                                               ; work         ;
;    |sld_hub:sld_hub_inst|                                                                            ; 104 (65)          ; 73 (45)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_hub:sld_hub_inst                                                                                                                                                                                                                                                                          ; work         ;
;       |sld_rom_sr:hub_info_reg|                                                                      ; 22 (22)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg                                                                                                                                                                                                                                                  ; work         ;
;       |sld_shadow_jsm:shadow_jsm|                                                                    ; 17 (17)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm                                                                                                                                                                                                                                                ; work         ;
;    |sld_signaltap:auto_signaltap_0|                                                                  ; 248 (1)           ; 378 (0)      ; 1792        ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                                                                ; work         ;
;       |sld_signaltap_impl:sld_signaltap_body|                                                        ; 247 (21)          ; 378 (110)    ; 1792        ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body                                                                                                                                                                                                                          ; work         ;
;          |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|                            ; 17 (0)            ; 46 (46)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem                                                                                                                                                           ; work         ;
;             |lpm_decode:wdecoder|                                                                    ; 2 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder                                                                                                                                       ; work         ;
;                |decode_rqf:auto_generated|                                                           ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_rqf:auto_generated                                                                                                             ; work         ;
;             |lpm_mux:mux|                                                                            ; 15 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux                                                                                                                                               ; work         ;
;                |mux_aoc:auto_generated|                                                              ; 15 (15)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_aoc:auto_generated                                                                                                                        ; work         ;
;          |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|                                           ; 0 (0)             ; 0 (0)        ; 1792        ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram                                                                                                                                                                          ; work         ;
;             |altsyncram_hps3:auto_generated|                                                         ; 0 (0)             ; 0 (0)        ; 1792        ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_hps3:auto_generated                                                                                                                                           ; work         ;
;          |lpm_shiftreg:segment_offset_config_deserialize|                                            ; 0 (0)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize                                                                                                                                                                           ; work         ;
;          |lpm_shiftreg:status_register|                                                              ; 17 (17)           ; 17 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:status_register                                                                                                                                                                                             ; work         ;
;          |sld_buffer_manager:sld_buffer_manager_inst|                                                ; 62 (62)           ; 44 (44)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst                                                                                                                                                                               ; work         ;
;          |sld_ela_control:ela_control|                                                               ; 34 (1)            ; 86 (1)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control                                                                                                                                                                                              ; work         ;
;             |lpm_shiftreg:trigger_config_deserialize|                                                ; 0 (0)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize                                                                                                                                                      ; work         ;
;             |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 28 (0)            ; 70 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm                                                                                                       ; work         ;
;                |lpm_shiftreg:trigger_condition_deserialize|                                          ; 0 (0)             ; 42 (42)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize                                                            ; work         ;
;                |sld_mbpmg:\trigger_modules_gen:0:trigger_match|                                      ; 28 (0)            ; 28 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match                                                        ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1  ; work         ;
;             |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|                          ; 5 (5)             ; 11 (1)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity                                                                                                                                ; work         ;
;                |lpm_shiftreg:trigger_config_deserialize|                                             ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize                                                                                        ; work         ;
;          |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|          ; 76 (10)           ; 60 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst                                                                                                                                         ; work         ;
;             |lpm_counter:\adv_point_3_and_more:advance_pointer_counter|                              ; 6 (0)             ; 4 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter                                                                               ; work         ;
;                |cntr_rbi:auto_generated|                                                             ; 6 (6)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_rbi:auto_generated                                                       ; work         ;
;             |lpm_counter:read_pointer_counter|                                                       ; 7 (0)             ; 7 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter                                                                                                        ; work         ;
;                |cntr_02j:auto_generated|                                                             ; 7 (7)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_02j:auto_generated                                                                                ; work         ;
;             |lpm_counter:status_advance_pointer_counter|                                             ; 6 (0)             ; 4 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter                                                                                              ; work         ;
;                |cntr_sbi:auto_generated|                                                             ; 6 (6)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_sbi:auto_generated                                                                      ; work         ;
;             |lpm_counter:status_read_pointer_counter|                                                ; 3 (0)             ; 1 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter                                                                                                 ; work         ;
;                |cntr_gui:auto_generated|                                                             ; 3 (3)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_gui:auto_generated                                                                         ; work         ;
;             |lpm_shiftreg:info_data_shift_out|                                                       ; 15 (15)           ; 15 (15)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out                                                                                                        ; work         ;
;             |lpm_shiftreg:ram_data_shift_out|                                                        ; 14 (14)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out                                                                                                         ; work         ;
;             |lpm_shiftreg:status_data_shift_out|                                                     ; 15 (15)           ; 15 (15)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out                                                                                                      ; work         ;
;          |sld_rom_sr:crc_rom_sr|                                                                     ; 20 (20)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr                                                                                                                                                                                                    ; work         ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name                                                                                                                                                           ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF  ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_hps3:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128          ; 14           ; 128          ; 14           ; 1792 ; None ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+


Encoding Type:  One-Hot
+-------------------------------+
; State Machine - |signaltap|ps ;
+------+------+------+----------+
; Name ; ps.A ; ps.C ; ps.B     ;
+------+------+------+----------+
; ps.A ; 0    ; 0    ; 0        ;
; ps.B ; 1    ; 0    ; 1        ;
; ps.C ; 1    ; 1    ; 0        ;
+------+------+------+----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                            ;
+-------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                   ; Reason for Removal                                                                                                                                          ;
+-------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|segment_shift_clk_ena                                                      ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_enable_delayed                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[0] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[0] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[1] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[1] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[2] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[2] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[3] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[3] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[4] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[4] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[5] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[5] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[6] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[6] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|current_offset_delayed[0]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[0]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|current_offset_delayed[1]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[1]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|current_offset_delayed[2]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[2]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|current_offset_delayed[3]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[3]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|current_offset_delayed[4]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[4]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|current_offset_delayed[5]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[5]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|current_offset_delayed[6]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[6]                                            ;
; Total Number of Removed Registers = 15                                                                                                          ;                                                                                                                                                             ;
+-------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 462   ;
; Number of registers using Synchronous Clear  ; 13    ;
; Number of registers using Synchronous Load   ; 17    ;
; Number of registers using Asynchronous Clear ; 207   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 239   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                      ; Fan out ;
+----------------------------------------------------------------------------------------------------------------------------------------+---------+
; shift_reg_bits[0]                                                                                                                      ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[7] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[1] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[5] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[4] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[3] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[6] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0] ; 1       ;
; sld_hub:sld_hub_inst|tdo                                                                                                               ; 2       ;
; Total number of inverted registers = 10                                                                                                ;         ;
+----------------------------------------------------------------------------------------------------------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------+
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1]      ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[1]                      ;
; 12:1               ; 4 bits    ; 32 LEs        ; 28 LEs               ; 4 LEs                  ; Yes        ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3]                           ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; No         ; |signaltap|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~12 ;
; 5:1                ; 8 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |signaltap|sld_hub:sld_hub_inst|irf_reg[1][0]                                                                                              ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |signaltap|sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3]                                                                    ;
; 6:1                ; 7 bits    ; 28 LEs        ; 7 LEs                ; 21 LEs                 ; Yes        ; |signaltap|sld_hub:sld_hub_inst|irsr_reg[4]                                                                                                ;
; 6:1                ; 8 bits    ; 32 LEs        ; 8 LEs                ; 24 LEs                 ; Yes        ; |signaltap|sld_hub:sld_hub_inst|shadow_irf_reg[1][3]                                                                                       ;
; 20:1               ; 4 bits    ; 52 LEs        ; 36 LEs               ; 16 LEs                 ; Yes        ; |signaltap|sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ;
+---------------------------------+-------+------+--------------------------------------------+
; Assignment                      ; Value ; From ; To                                         ;
+---------------------------------+-------+------+--------------------------------------------+
; NOT_GATE_PUSH_BACK              ; OFF   ; -    ; -                                          ;
; POWER_UP_LEVEL                  ; LOW   ; -    ; -                                          ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                          ;
+---------------------------------+-------+------+--------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst ;
+--------------------+-------+------+----------------------------------------------------------------------------------------------------+
; Assignment         ; Value ; From ; To                                                                                                 ;
+--------------------+-------+------+----------------------------------------------------------------------------------------------------+
; NOT_GATE_PUSH_BACK ; ON    ; -    ; modified_post_count[4]                                                                             ;
; NOT_GATE_PUSH_BACK ; ON    ; -    ; modified_post_count[3]                                                                             ;
; NOT_GATE_PUSH_BACK ; ON    ; -    ; modified_post_count[2]                                                                             ;
; NOT_GATE_PUSH_BACK ; ON    ; -    ; modified_post_count[1]                                                                             ;
; NOT_GATE_PUSH_BACK ; ON    ; -    ; modified_post_count[0]                                                                             ;
; NOT_GATE_PUSH_BACK ; ON    ; -    ; modified_post_count[5]                                                                             ;
; NOT_GATE_PUSH_BACK ; ON    ; -    ; modified_post_count[6]                                                                             ;
; NOT_GATE_PUSH_BACK ; ON    ; -    ; modified_post_count[7]                                                                             ;
+--------------------+-------+------+----------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_hps3:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                           ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                            ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:\adv_point_3_and_more:advance_pointer_counter ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                                                                                                          ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                                                                                                                           ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                                                                                                           ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                                                                                                                           ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:read_pointer_counter ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                                                                                 ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                                                                                                  ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                                                                                  ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                                                                                                  ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_advance_pointer_counter ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                                                                                           ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                                                                                                            ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                                                                                            ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                                                                                                            ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_read_pointer_counter ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                                                                                                         ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                                                                                         ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                                                                                                         ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr ;
+----------------------+-------+------+-----------------------------------------------------------------------------+
; Assignment           ; Value ; From ; To                                                                          ;
+----------------------+-------+------+-----------------------------------------------------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                                                                           ;
+----------------------+-------+------+-----------------------------------------------------------------------------+


+-------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst           ;
+------------------------------+-------+------+---------+
; Assignment                   ; Value ; From ; To      ;
+------------------------------+-------+------+---------+
; IGNORE_LCELL_BUFFERS         ; OFF   ; -    ; -       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF   ; -    ; -       ;
; NOT_GATE_PUSH_BACK           ; OFF   ; -    ; clr_reg ;
; POWER_UP_LEVEL               ; LOW   ; -    ; clr_reg ;
+------------------------------+-------+------+---------+


+---------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg ;
+----------------------+-------+------+-------------------------------+
; Assignment           ; Value ; From ; To                            ;
+----------------------+-------+------+-------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                             ;
+----------------------+-------+------+-------------------------------+


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |signaltap ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type                                             ;
+----------------+-------+--------------------------------------------------+
; A              ; 00    ; Unsigned Binary                                  ;
; B              ; 01    ; Unsigned Binary                                  ;
; C              ; 10    ; Unsigned Binary                                  ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0                                                    ;
+-------------------------------------------------+-----------------------------------------------------------------+----------------+
; Parameter Name                                  ; Value                                                           ; Type           ;
+-------------------------------------------------+-----------------------------------------------------------------+----------------+
; lpm_type                                        ; sld_signaltap                                                   ; String         ;
; sld_node_info                                   ; 805334528                                                       ; Untyped        ;
; SLD_IP_VERSION                                  ; 6                                                               ; Signed Integer ;
; SLD_IP_MINOR_VERSION                            ; 0                                                               ; Signed Integer ;
; SLD_COMMON_IP_VERSION                           ; 0                                                               ; Signed Integer ;
; sld_data_bits                                   ; 14                                                              ; Untyped        ;
; sld_trigger_bits                                ; 14                                                              ; Untyped        ;
; SLD_NODE_CRC_BITS                               ; 32                                                              ; Signed Integer ;
; sld_node_crc_hiword                             ; 53125                                                           ; Untyped        ;
; sld_node_crc_loword                             ; 45565                                                           ; Untyped        ;
; SLD_INCREMENTAL_ROUTING                         ; 0                                                               ; Signed Integer ;
; sld_sample_depth                                ; 128                                                             ; Untyped        ;
; sld_segment_size                                ; 128                                                             ; Untyped        ;
; SLD_RAM_BLOCK_TYPE                              ; AUTO                                                            ; String         ;
; sld_state_bits                                  ; 11                                                              ; Untyped        ;
; sld_buffer_full_stop                            ; 1                                                               ; Untyped        ;
; SLD_MEM_ADDRESS_BITS                            ; 7                                                               ; Signed Integer ;
; SLD_DATA_BIT_CNTR_BITS                          ; 4                                                               ; Signed Integer ;
; sld_trigger_level                               ; 1                                                               ; Untyped        ;
; sld_trigger_in_enabled                          ; 0                                                               ; Untyped        ;
; sld_advanced_trigger_entity                     ; basic,1,                                                        ; Untyped        ;
; sld_trigger_level_pipeline                      ; 1                                                               ; Untyped        ;
; sld_enable_advanced_trigger                     ; 0                                                               ; Untyped        ;
; SLD_ADVANCED_TRIGGER_1                          ; NONE                                                            ; String         ;
; SLD_ADVANCED_TRIGGER_2                          ; NONE                                                            ; String         ;
; SLD_ADVANCED_TRIGGER_3                          ; NONE                                                            ; String         ;
; SLD_ADVANCED_TRIGGER_4                          ; NONE                                                            ; String         ;
; SLD_ADVANCED_TRIGGER_5                          ; NONE                                                            ; String         ;
; SLD_ADVANCED_TRIGGER_6                          ; NONE                                                            ; String         ;
; SLD_ADVANCED_TRIGGER_7                          ; NONE                                                            ; String         ;
; SLD_ADVANCED_TRIGGER_8                          ; NONE                                                            ; String         ;
; SLD_ADVANCED_TRIGGER_9                          ; NONE                                                            ; String         ;
; SLD_ADVANCED_TRIGGER_10                         ; NONE                                                            ; String         ;
; sld_inversion_mask_length                       ; 63                                                              ; Untyped        ;
; sld_inversion_mask                              ; 000000000000000000000000000000000000000000000000000000000000000 ; Untyped        ;
; sld_power_up_trigger                            ; 0                                                               ; Untyped        ;
; SLD_STATE_FLOW_MGR_ENTITY                       ; state_flow_mgr_entity.vhd                                       ; String         ;
; sld_state_flow_use_generated                    ; 0                                                               ; Untyped        ;
; sld_current_resource_width                      ; 1                                                               ; Untyped        ;
; sld_attribute_mem_mode                          ; OFF                                                             ; Untyped        ;
; SLD_STORAGE_QUALIFIER_BITS                      ; 1                                                               ; Signed Integer ;
; SLD_STORAGE_QUALIFIER_GAP_RECORD                ; 0                                                               ; Signed Integer ;
; SLD_STORAGE_QUALIFIER_MODE                      ; OFF                                                             ; String         ;
; SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION ; 0                                                               ; Signed Integer ;
; sld_storage_qualifier_inversion_mask_length     ; 0                                                               ; Untyped        ;
; SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY ; basic                                                           ; String         ;
; SLD_STORAGE_QUALIFIER_PIPELINE                  ; 0                                                               ; Signed Integer ;
+-------------------------------------------------+-----------------------------------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst         ;
+--------------------------+----------------------------------+-----------------+
; Parameter Name           ; Value                            ; Type            ;
+--------------------------+----------------------------------+-----------------+
; sld_hub_ip_version       ; 1                                ; Untyped         ;
; sld_hub_ip_minor_version ; 4                                ; Untyped         ;
; sld_common_ip_version    ; 0                                ; Untyped         ;
; device_family            ; Cyclone II                       ; Untyped         ;
; n_nodes                  ; 1                                ; Untyped         ;
; n_sel_bits               ; 1                                ; Untyped         ;
; n_node_ir_bits           ; 8                                ; Untyped         ;
; node_info                ; 00110000000000000110111000000000 ; Unsigned Binary ;
; compilation_mode         ; 1                                ; Untyped         ;
; BROADCAST_FEATURE        ; 1                                ; Signed Integer  ;
; FORCE_IR_CAPTURE_FEATURE ; 1                                ; Signed Integer  ;
+--------------------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                                           ;
+----------------+------------------+---------------------+------------------+--------------+----------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; Instance Index ; Instance Name    ; Trigger Input Width ; Data Input Width ; Sample Depth ; Segments ; Trigger Flow Control ; Trigger Conditions ; Advanced Trigger Conditions ; Trigger In Used ; Trigger Out Used ; Power-Up Trigger Enabled ;
+----------------+------------------+---------------------+------------------+--------------+----------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; 0              ; auto_signaltap_0 ; 14                  ; 14               ; 128          ; 1        ; sequential           ; 1                  ; 0                           ; no              ; no               ; no                       ;
+----------------+------------------+---------------------+------------------+--------------+----------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Connections to In-System Debugging Instance "auto_signaltap_0"                                                    ;
+----------+---------------+-----------+----------------+-------------------+-----------------------------+---------+
; Name     ; Type          ; Status    ; Partition Name ; Netlist Type Used ; Actual Connection           ; Details ;
+----------+---------------+-----------+----------------+-------------------+-----------------------------+---------+
; KEY[0]   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; KEY[0]                      ; N/A     ;
; KEY[0]   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; KEY[0]                      ; N/A     ;
; KEY[1]   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; KEY[1]                      ; N/A     ;
; KEY[1]   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; KEY[1]                      ; N/A     ;
; LEDG[0]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[0]~_wirecell ; N/A     ;
; LEDG[0]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[0]~_wirecell ; N/A     ;
; LEDG[1]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[1]           ; N/A     ;
; LEDG[1]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[1]           ; N/A     ;
; LEDG[2]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[2]           ; N/A     ;
; LEDG[2]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[2]           ; N/A     ;
; LEDG[3]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[3]           ; N/A     ;
; LEDG[3]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[3]           ; N/A     ;
; LEDG[4]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[4]           ; N/A     ;
; LEDG[4]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[4]           ; N/A     ;
; LEDG[5]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[5]           ; N/A     ;
; LEDG[5]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[5]           ; N/A     ;
; LEDG[6]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[6]           ; N/A     ;
; LEDG[6]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[6]           ; N/A     ;
; LEDG[7]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[7]           ; N/A     ;
; LEDG[7]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; shift_reg_bits[7]           ; N/A     ;
; enable   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; ps.B                        ; N/A     ;
; enable   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; ps.B                        ; N/A     ;
; ps.A     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; ps.A~_wirecell              ; N/A     ;
; ps.A     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; ps.A~_wirecell              ; N/A     ;
; ps.B     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; ps.B                        ; N/A     ;
; ps.B     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; ps.B                        ; N/A     ;
; ps.C     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; ps.C                        ; N/A     ;
; ps.C     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; ps.C                        ; N/A     ;
; CLOCK_50 ; post-fitting  ; connected ; Top            ; post-synthesis    ; CLOCK_50                    ; N/A     ;
+----------+---------------+-----------+----------------+-------------------+-----------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Mon Jul 20 16:26:56 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off signaltap -c signaltap
Info: Found 1 design units, including 1 entities, in source file signaltap.v
    Info: Found entity 1: signaltap
Info: Elaborating entity "signaltap" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hps3.tdf
    Info: Found entity 1: altsyncram_hps3
Info: Found 1 design units, including 1 entities, in source file db/mux_aoc.tdf
    Info: Found entity 1: mux_aoc
Info: Found 1 design units, including 1 entities, in source file db/decode_rqf.tdf
    Info: Found entity 1: decode_rqf
Info: Found 1 design units, including 1 entities, in source file db/cntr_rbi.tdf
    Info: Found entity 1: cntr_rbi
Info: Found 1 design units, including 1 entities, in source file db/cmpr_8cc.tdf
    Info: Found entity 1: cmpr_8cc
Info: Found 1 design units, including 1 entities, in source file db/cntr_02j.tdf
    Info: Found entity 1: cntr_02j
Info: Found 1 design units, including 1 entities, in source file db/cntr_sbi.tdf
    Info: Found entity 1: cntr_sbi
Info: Found 1 design units, including 1 entities, in source file db/cntr_gui.tdf
    Info: Found entity 1: cntr_gui
Info: Found 1 design units, including 1 entities, in source file db/cmpr_5cc.tdf
    Info: Found entity 1: cmpr_5cc
Info: Analysis and Synthesis generated SignalTap II or debug node instance "auto_signaltap_0"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Succesfully connected in-system debug instance "auto_signaltap_0" to all 29 required data inputs, trigger inputs, acquisition clocks, and dynamic pins
Info: Implemented 647 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 9 output pins
    Info: Implemented 617 logic cells
    Info: Implemented 14 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 206 megabytes
    Info: Processing ended: Mon Jul 20 16:27:13 2009
    Info: Elapsed time: 00:00:17
    Info: Total CPU time (on all processors): 00:00:13


