| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| my_system|custom_system_reset_clk_domain_synch |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| my_system|the_switches |
53 |
0 |
38 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| my_system|the_switches_avalon_parallel_port_slave |
102 |
0 |
2 |
0 |
80 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| my_system|the_red_LEDs |
43 |
0 |
25 |
0 |
42 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| my_system|the_red_LEDs_avalon_parallel_port_slave |
102 |
0 |
2 |
0 |
80 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| my_system|the_onchip_mem|the_altsyncram|auto_generated |
49 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| my_system|the_onchip_mem |
50 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| my_system|the_onchip_mem_s1 |
132 |
1 |
4 |
1 |
91 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| my_system|the_cpu |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| my_system|the_cpu_instruction_master |
105 |
14 |
15 |
14 |
63 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| my_system|the_cpu_data_master |
184 |
14 |
24 |
14 |
62 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| my_system|the_cpu_jtag_debug_module |
134 |
1 |
4 |
1 |
93 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| my_system |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |