dual_processor_system

generated 2009.07.20.18:27:01

Overview

  clk  dual_processor_system
Processors
   cpu_one Nios II 9.0
   cpu_two Nios II 9.0
Peripherals
   cpu_one altera_nios2 9.0
   onchip_mem_one altera_avalon_onchip_memory2 9.0
   jtag_uart_one altera_avalon_jtag_uart 9.0
   bridge_one altera_up_avalon_to_external_bus_bridge 9.0
   cpu_two altera_nios2 9.0
   onchip_mem_two altera_avalon_onchip_memory2 9.0
   jtag_uart_two altera_avalon_jtag_uart 9.0
   bridge_two altera_up_avalon_to_external_bus_bridge 9.0
cpu_one cpu_two
 instruction_master  data_master  instruction_master  data_master
  cpu_one
jtag_debug_module  0x00080000 0x00080000
  onchip_mem_one
s1  0x00084000 0x00084000
  jtag_uart_one
avalon_jtag_slave  0x00088000
  bridge_one
avalon_slave  0x00000000
  cpu_two
jtag_debug_module  0x00080000 0x00080000
  onchip_mem_two
s1  0x00084000 0x00084000
  jtag_uart_two
avalon_jtag_slave  0x00088000
  bridge_two
avalon_slave  0x00000000

clk

clock_source v9.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
  

Software Assignments

(none)

cpu_one

altera_nios2 v9.0
clk clk   cpu_one
  clk
instruction_master   onchip_mem_one
  s1
data_master  
  s1
data_master   jtag_uart_one
  avalon_jtag_slave
d_irq  
  irq
data_master   bridge_one
  avalon_slave
d_irq  
  interrupt
d_irq   jtag_uart_two
  irq
d_irq   bridge_two
  interrupt


Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSetsPresent false
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_numShadowRegisterSets 1
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_eicPresent false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_autoAssignNumShadowRegisterSets true
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave onchip_mem_one.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
impl Small
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave onchip_mem_one.s1
exceptionOffset 32
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
cpuReset false
cpuID 0
clockFrequency 50000000
breakSlave cpu_one.jtag_debug_module
breakOffset 32
  

Software Assignments

CPU_IMPLEMENTATION "small"
CPU_FREQ 50000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x84020
RESET_ADDR 0x84000
BREAK_ADDR 0x80020
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 20
DATA_ADDR_WIDTH 20

onchip_mem_one

altera_avalon_onchip_memory2 v9.0
clk clk   onchip_mem_one
  clk1
cpu_one instruction_master  
  s1
data_master  
  s1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort false
initMemContent true
initializationFileName onchip_mem_one
instanceID NONE
memorySize 4096
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_mem_one"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 4096u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

jtag_uart_one

altera_avalon_jtag_uart v9.0
clk clk   jtag_uart_one
  clk
cpu_one data_master  
  avalon_jtag_slave
d_irq  
  irq
cpu_two d_irq  
  irq


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
writeBufferDepth 64
writeIRQThreshold 8
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

bridge_one

altera_up_avalon_to_external_bus_bridge v9.0
clk clk   bridge_one
  clock_reset
cpu_one data_master  
  avalon_slave
d_irq  
  interrupt
cpu_two d_irq  
  interrupt


Parameters

addr_size 512
addr_size_multiplier Kbytes
data_size 32
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
  

Software Assignments

(none)

cpu_two

altera_nios2 v9.0
clk clk   cpu_two
  clk
d_irq   jtag_uart_one
  irq
d_irq   bridge_one
  interrupt
instruction_master   onchip_mem_two
  s1
data_master  
  s1
d_irq   jtag_uart_two
  irq
data_master  
  avalon_jtag_slave
data_master   bridge_two
  avalon_slave
d_irq  
  interrupt


Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSetsPresent false
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_numShadowRegisterSets 1
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_eicPresent false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_autoAssignNumShadowRegisterSets true
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave onchip_mem_two.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
impl Small
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave onchip_mem_two.s1
exceptionOffset 32
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
cpuReset false
cpuID 0
clockFrequency 50000000
breakSlave cpu_two.jtag_debug_module
breakOffset 32
  

Software Assignments

CPU_IMPLEMENTATION "small"
CPU_FREQ 50000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x84020
RESET_ADDR 0x84000
BREAK_ADDR 0x80020
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x1
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 20
DATA_ADDR_WIDTH 20

onchip_mem_two

altera_avalon_onchip_memory2 v9.0
clk clk   onchip_mem_two
  clk1
cpu_two instruction_master  
  s1
data_master  
  s1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort false
initMemContent true
initializationFileName onchip_mem_two
instanceID NONE
memorySize 4096
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_mem_two"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 4096u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

jtag_uart_two

altera_avalon_jtag_uart v9.0
clk clk   jtag_uart_two
  clk
cpu_one d_irq  
  irq
cpu_two d_irq  
  irq
data_master  
  avalon_jtag_slave


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
writeBufferDepth 64
writeIRQThreshold 8
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

bridge_two

altera_up_avalon_to_external_bus_bridge v9.0
clk clk   bridge_two
  clock_reset
cpu_two data_master  
  avalon_slave
d_irq  
  interrupt
cpu_one d_irq  
  interrupt


Parameters

addr_size 512
addr_size_multiplier Kbytes
data_size 32
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
  

Software Assignments

(none)

generation took 0.02 seconds
rendering took 6.41 seconds